• Available in Pb-free and non Pb-free 28-pin (300-Mil)
Molded SOJ, 28-pin (300-Mil) DIP and 28-pin TSOP I
packages
General Description
The CY7C199C is a high-performance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an
asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected.
See the Truth Table in this data sheet for a complete
description of read and write modes
Logic Block Diagram
Input Buffer
Row Decoder
RAM Array
ARRAY
32K x 8
Sense Amps
I/Ox
CE
Column Decoder
Power
Down
Circuit
WE
OE
A
X
X
Product Portfolio
12 ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current (L)
12
85
15 ns
15
80
500
20 ns
20
75
Unit
ns
mA
µA
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05408 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 3, 2006
[+] Feedback
CY7C199C
Pin Layout and Specifications
28 DIP (6.9 x 35.6 x 3.5 mm)
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 TSOP I (8 x 13.4 mm)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
V
SS
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
28 SOJ
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
Document #: 38-05408 Rev. *C
Page 2 of 13
[+] Feedback
CY7C199C
Pin Description
Pin
A
X
CE
I/O
X
OE
V
CC
V
SS
WE
Type
Input
Control
Input or
Output
Control
Supply
Supply
Control
Description
Address Inputs
Chip Enable
Data
Input/Outputs
Output Enable
Power (5.0V)
Ground
Write Enable
DIP
1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
21, 23, 24, 25, 26
20
11, 12, 13, 15, 16, 17,
18, 19
22
28
14
27
SOJ
1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
21, 23, 24, 25, 26
20
11, 12, 13, 15, 16, 17, 18,
19
22
28
14
27
TSOP I
2, 3, 4, 5, 8, 9, 10, 11, 12,
13, 14, 15, 16, 17, 28
27
18, 19, 20, 22, 23, 24, 25,
26
1
7
21
6
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Parameter
T
STG
T
AMB
V
CC
V
IN
, V
OUT
I
OUT
V
ESD
I
LU
Storage Temperature
Ambient Temperature with Power Applied (i.e., case temperature)
Core Supply Voltage Relative to V
SS
DC Voltage Applied to any Pin Relative to V
SS
Output Short-Circuit Current
Static Discharge Voltage (per MIL-STD-883, Method 3015)
Latch-up Current
Description
Value
–65 to +150
–55 to +125
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
20
> 2001
> 200
Unit
°C
°C
V
V
mA
V
mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature (T
A
)
0°C to 70°C
–40°C to 85°C
Voltage Range (V
CC
)
5.0V ± 10%
5.0V ± 10%
DC Electrical Characteristics
Over the Operating Range
[2]
12 ns
Parameter
V
IH
V
IL
V
OH
V
OL
I
IX
I
OZ
I
CC
I
SB1
Description
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
GND
≤
V
I
≤
V
CC
GND
≤
V
I
≤
V
CC
, Output
Disabled
V
CC
= Max., I
OUT
= 0 mA,
f = F
MAX
= 1/t
RC
L
10
L
–5
–5
Condition
Min.
2.2
–0.5
2.4
0.4
+5
+5
85
30
–5
–5
Max.
V
CC
+ 0.3
0.8
Min.
2.2
–0.5
2.4
0.4
+5
+5
80
30
10
10
500
10
–5
–5
15 ns
Max.
V
CC
+ 0.3
0.8
Min.
2.2
–0.5
2.4
0.4
+5
+5
75
30
20 ns
Max.
V
CC
+ 0.3
0.8
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
µA
Automatic CE
Max. V
CC
, CE
≥
V
IH
, V
IN
≥
Power-down Current V
IH
or V
IN
≤
V
IL
, f = F
MAX
TTL Inputs
Automatic CE
Max. V
CC
, CE
≥
V
CC
– 0.3V,
Power-down Current V
IN
≥
V
CC
– 0.3V, or V
IN
≤
0.3V, f = 0
CMOS Inputs
I
SB2
Note:
2. V
IL
(min) = –2.0V for pulse durations of less than 20 ns.
Document #: 38-05408 Rev. *C
Page 3 of 13
[+] Feedback
CY7C199C
Capacitance
[3]
Max.
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
ALL – PACKAGES
8
8
Unit
pF
Thermal Resistance
[4]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Conditions
Still Air, soldered on a 3 × 4.5
square inch, two–layer printed
circuit board
TSOP I
88.6
21.94
SOJ
79
41.42
DIP
69.33
31.62
Unit
°C/W
AC Test Loads and Waveforms
V
CC
C1
INCLUDING
JIG AND
SCOPE
R1
V
CC
R2
C2
INCLUDING
JIGAND
SCOPE
R1
3.0V
R2
GND
10%
ALL INPUT PULSES
90%
90%
10%
≤
1V/ns
≤
1V/ns
(a)
(b)
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
R
th
V
T
output load
output load for
t
HZOE,
t
HZCE,
t
HZWE
Notes:
3. Tested initially and after any design or process change that may affect these parameters.
4. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
Document #: 38-05408 Rev. *C
Page 4 of 13
[+] Feedback
CY7C199C
AC Test Conditions
Parameter
C1
C2
R1
R2
R
TH
V
TH
Capacitor 1
Capacitor 2
Resistor 1
Resistor 2
Resistor Thevenin
Voltage Thevenin
Description
Nom.
30
5
480
255
167
1.73
Unit
pF
Ω
V
AC Electrical Characteristics
[5, 6, 7]
12 ns
Parameter
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Addres Change
CE to Data Valid
OE to Data Valid
OE to Low Z
OE to High Z
CE to Low Z
CE to High Z
CE to Power-up
CE to Power-down
Write Cycle Time
CE to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
3
12
9
9
0
0
8
8
0
7
3
0
12
15
10
10
0
0
9
9
0
7
3
3
5
0
15
20
15
15
0
0
15
10
0
10
0
5
3
7
0
20
3
12
5
0
7
3
9
Min
12
12
3
15
7
0
9
Max
Min
15
15
3
20
9
15 ns
Max
Min
20
20
20 ns
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
5. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
6. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set–up and hold timing should be referenced to the leading edge of the signal that terminates the write.
7. t
HZOE
, t
HZCE
, t
HZWE
are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
