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MM74HC08 — Quad 2-Input AND Gate
February 2008
MM74HC08
Quad 2-Input AND Gate
Features
■
Typical propagation delay: 7ns (t
PHL
), 12ns (t
PLH
)
■
Fanout of 10 LS-TTL loads
■
Quiescent power consumption: 2µA maximum at
General Description
The MM74HC08 AND gates utilize advanced silicon-
gate CMOS technology to achieve operating speeds
similar to LS-TTL gates with the low power consumption
of standard CMOS integrated circuits. The HC08 has
buffered outputs, providing high noise immunity and the
ability to drive 10 LS-TTL loads. The 74HC logic family is
functionally as well as pin-out compatible with the stan-
dard 74LS logic family. All inputs are protected from
damage due to static discharge by internal diode clamps
to V
CC
and ground.
room temperature
■
Low input current: 1µA maximum
Ordering Information
Package
Order Number Number
MM74HC08M
MM74HC08SJ
MM74HC08MTC
MM74HC08N
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel except for N14A. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Top View
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
MM74HC08 — Quad 2-Input AND Gate
Absolute Maximum Ratings
(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
, I
OK
I
OUT
I
CC
T
STG
P
D
Supply Voltage
DC Input Voltage
DC Output Voltage
Clamp Diode Current
DC Output Current, per pin
Parameter
Rating
–0.5 to +7.0V
–1.5 to V
CC
+1.5V
–0.5 to V
CC
+0.5V
±20mA
±25mA
±50mA
–65°C to +150°C
600mW
500mW
260°C
DC V
CC
or GND Current, per pin
Storage Temperature Range
Power Dissipation
Note 2
S.O. Package only
Lead Temperature (Soldering 10 seconds)
T
L
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Supply Voltage
DC Input or Output Voltage
Parameter
Min.
2
0
–40
Max.
6
V
CC
+85
1000
500
400
Units
V
V
°C
ns
ns
ns
Operating Temperature Range
Input Rise or Fall Times
V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
2
MM74HC08 — Quad 2-Input AND Gate
DC Electrical Characteristics
(3)
T
A
=
25°C
Symbol
V
IH
T
A
=
–40°C
to 85°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
20
T
A
=
–55°C
to 125°C
Units
V
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
40
µA
µA
V
V
V
Parameter
Minimum HIGH Level
Input Voltage
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
Conditions
Typ.
1.5
3.15
4.2
0.5
1.35
1.8
Guaranteed Limits
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
,
|I
OUT
|
≤
20µA
V
IN
=
V
IH
,
|I
OUT
|
≤
4.0mA
V
IN
=
V
IH
,
|I
OUT
|
≤
5.2mA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
20µA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
4.0mA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
5.2mA
V
IN
=
V
CC
or GND
V
IN
=
V
CC
or GND,
I
OUT
=
0µA
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
2.0
V
OL
Maximum LOW Level
Output Voltage
2.0
4.5
6.0
4.5
6.0
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
6.0
6.0
Note:
3. For a power supply of 5V ±10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V
values should be used when designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V
respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current (I
IN
, I
CC
, and I
OZ
) occur for CMOS at
the higher voltage and so the 6.0V values should be used.
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
3
MM74HC08 — Quad 2-Input AND Gate
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25°C, C
L
=
15pF, t
r
=
t
f
=
6ns
Symbol
t
PHL
t
PLH
Parameter
Maximum Propagation Delay,
Output HIGH-to-LOW
Maximum Propagation Delay,
Output LOW-to-HIGH
Conditions
Typ.
12
7
Guaranteed
Limit
20
15
Units
ns
ns
AC Electrical Characteristics
V
CC
=
2.0V to 6.0V, C
L
=
50pF, t
r
=
t
f
=
6ns (unless otherwise specified)
T
A
=
25°C
Symbol
t
PHL
T
A
=
–40°C
to 125°C
Units
ns
175
35
30
134
27
23
110
22
19
pF
ns
ns
Parameter
Maximum Propagation Delay,
Output HIGH-to-LOW
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Conditions
Typ.
77
15
13
30
10
8
30
8
7
Guaranteed Limits
121
24
20
90
18
15
75
15
13
t
PLH
Maximum Propagation Delay,
Output LOW-to-HIGH
t
TLH
, t
THL
Maximum Output Rise and Fall
Time
C
PD
C
IN
Power Dissipation
Capacitance
(4)
Maximum Input Capacitance
(per gate)
38
4
10
10
pF
Note:
4. C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC2
f + I
CC
V
CC
, and the no load dynamic
current consumption, I
S
=
C
PD
V
CC
f + I
CC
.
©1983 Fairchild Semiconductor Corporation
MM74HC08 Rev. 1.4.0
www.fairchildsemi.com
4
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