CMOS Static RAM
1 Meg (128K x 8-Bit)
Features
Description
IDT71024S
◆
◆
◆
◆
◆
◆
◆
128K x 8 advanced high-speed CMOS static RAM
Commercial (0°C to +70°C), Industrial (–40°C to +85°C)
Equal access and cycle times
— Commercial and Industrial: 12/15/20ns
Two Chip Selects plus one Output Enable pin
Bidirectional inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 300 and 400 mil Plastic SOJ.
The IDT71024 is a 1,048,576-bit high-speed static RAM organized as
128K x 8. It is fabricated using high-performance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71024 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71024 are TTL-compat-
ible, and operation is from a single 5V supply. Fully static asynchro-
nous circuitry is used; no clocks or refreshes are required for
operation.
The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32-
pin 400 mil Plastic SOJ.
Functional Block Diagram
FEBRUARY 2013
1
©2012 Integrated Device Technology, Inc.
DSC-2964/19
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–0.5 to +7.0
–55 to +125
–55 to +125
1.25
50
Unit
V
o
o
C
C
W
mA
2964 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
SOJ
Top View
Capacitance
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
8
Unit
pF
pF
2964 tbl 03
Truth Table
(1,3)
Inputs
WE
X
X
X
X
H
H
L
CS
1
H
V
HC
(2)
X
X
L
L
L
CS
2
X
X
L
V
LC
(2)
H
H
H
OE
X
X
X
X
H
L
X
I/O
High-Z
High-Z
High-Z
High-Z
High-Z
DATA
OUT
DATA
IN
Function
Deselected – Standby (I
SB
)
Deselected – Standby (I
SB1
)
Deselected – Standby (I
SB
)
Deselected – Standby (I
SB1
)
Outputs Disabled
Read Data
Write Data
2964 tbl 01
C
IN
C
I/O
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
V
CC
+0.5
0.8
Unit
V
V
V
V
2964 tbl 04
NOTES:
1. H = V
IH
, L = V
IL
, X = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
–0.2V.
3. Other inputs
≥V
HC
or
≤V
LC.
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
GND
0V
0V
V
CC
5.0V ± 0.5V
5.0V ± 0.5V
2964 tbl 05
NOTE:
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
6.42
2
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(V
CC
= 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
IDT71024
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
1
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= –4mA, V
CC
= Min.
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2964 tbl 06
2.4
DC Electrical Characteristics
(1)
(V
CC
= 5.0V ± 10%, V
LC
= 0.2V, V
HC
= V
CC
– 0.2V)
71024S12
Symbol
I
CC
Parameters
Dynamic Operating Current,
CS
2
≥
V
IH
and
CS
1
≤
V
IL
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current (TTL Level)
CS
1
≥
V
IH
or CS
2
≤
V
IL
, Outputs Open,
V
CC
= Max., f=f
MAX
(2)
Full Standby Power Supply Current
(CMOS Level),
CS
1
≥
V
HC
or
CS
2
≤
V
LC
, Outputs Open,
V
CC
= Max., f = 0
(2)
, V
IN
≤
V
LC
or V
IN
≥
V
HC
Com'l.
160
Ind.
160
71024S15
Com'l.
155
Ind.
155
71024S20
Com'l.
140
Ind.
140
Unit
mA
I
SB
40
40
40
40
40
40
mA
I
SB1
10
10
10
10
10
10
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address
input lines are changing.
2964 tbl 07
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
2964 tbl 08
5V
480Ω
5V
480Ω
DATA
OUT
30pF
255Ω
DATA
OUT
5pF*
255Ω
2964 drw 04
*Including jig and scope capacitance.
2964 drw 03
Figure 1. AC Test Load
6.42
3
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71024S12
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
Write Cycle
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Write Cycle Time
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-Up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Output Active from End-of-Write
Write Enab le to Output in High-Z
12
10
10
0
8
0
7
0
3
0
—
—
—
—
—
—
—
—
—
5
15
12
12
0
12
0
8
0
3
0
—
—
—
—
—
—
—
—
—
5
20
15
15
0
15
0
9
0
4
0
—
—
—
—
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2964 tbl 09
71024S15
Min.
Max.
71024S20
Min.
Max.
Unit
Parameter
Min.
Max.
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Sele ct to Output in Low-Z
Chip Desele ct to Output in High-Z
Output Enable to Output Valid
Output Enab le to Output in Low-Z
Output Disab le to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
12
—
—
3
0
—
0
0
4
0
—
—
12
12
—
6
6
—
5
—
—
12
15
—
—
3
0
—
0
0
4
0
—
—
15
15
—
7
7
—
5
—
—
15
20
—
—
3
0
—
0
0
4
0
—
—
20
20
—
8
8
—
7
—
—
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42
4
IDT71024 CMOS Static RAM
1 Meg (128K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
Timing Waveform of Read Cycle No. 2
(1,2,4)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
1
is LOW, CS
2
is HIGH.
3. Address must be valid prior to or coincident with the later of
CS
1
transition LOW and CS
2
transition HIGH; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
6.42
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
