CAT24FC64
64K-Bit I
2
C Serial CMOS EEPROM
FEATURES
I
Fast mode I
2
C bus compatible*
I
Max clock frequency:
I
Industrial and extended
temperature ranges
I
5 ms max write cycle time
I
Write protect feature
I
1,000,000 program/erase cycles
I
100 year data retention
- 400KHz for VCC=2.5V to 5.5V
I
Schmitt trigger filtered inputs for noise suppression
I
Low power CMOS technology
I
64-byte page write buffer
I
Self-timed write cycle with auto-clear
– entire array protected when WP at V
IH
I
8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC
(EIAJ), 8-pin TSSOP and TDFN packages
DESCRIPTION
The CAT24FC64 is a 64K-bit Serial CMOS EEPROM
internally organized as 8,192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24FC64
features a 64-byte page write buffer. The device oper-
ates via the I
2
C bus serial interface and is available in 8-
pin DIP, SOIC, TSSOP and TDFN packages.
PIN CONFIGURATION
DIP Package (P, L, GL)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
TDFN Package (RD2, ZD2)
A0
1
A1
2
A2
3
VSS
4
8
VCC
7
WP
SOIC Package
(J, W, K, X, GW, GX)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
NC
i
D
c
s
VCC
WP
SCL
SDA
A0
A1
A2
VSS
TSSOP Package (U, Y, GY)
1
2
3
4
8
7
6
5
n
o
(Top View)
6
SCL
5
SDA
i
t
WP
SCL
SDA
u
n
VCC
VSS
SDA
WP
BLOCK DIAGRAM
EXTERNAL LOAD
d
e
DOUT
ACK
CONTROL
LOGIC
a
P
128
t
r
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
512
START/STOP
LOGIC
VCC
XDEC
EEPROM
128X512
Function
DATA IN STORAGE
Address Inputs
Serial Data/Address
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
Serial Clock
Write Protect
+2.5V to +5.5V Power Supply
Ground
No Connect
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1046, Rev. K
CAT24FC64
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END
T
DR
V
ZAP
I
LTH(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min
1,000,000
100
4000
100
Typ
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +5.5V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL
Parameter
Power Supply Current - Read
Power Supply Current - Write
Standby Current
Input Leakage Current
Test Conditions
Output Leakage Current
Input Low Voltage
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Z
WPL
Test
Conditions
V
I/O
= 0V
V
IN
= 0V
V
IN
≤
0.5V
V
IN
>0.7VxV
CC
5
500
Min
Typ
Max
8
6
70
Units
pF
pF
kΩ
kΩ
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP, A0, A1)
WP Input Impedance
WP Input Impedance
i
D
Input High Voltage
Output Low Voltage (V
CC
= +3.0V)
c
s
n
o
V
IN
= GND or V
CC
V
CC
=5V
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-0.5
V
CC
x 0.7
I
OL
= 3.0 mA
i
t
f
SCL
= 400 KHz
V
CC
=5V
f
SCL
= 400KHz
V
CC
=5V
u
n
Min
d
e
a
P
Max
Max
1
3
1
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
Cycles/Byte
Years
Volts
mA
t
r
mA
mA
µA
µA
µA
V
V
V
Typ
Units
Z
WPH
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parametesr are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Extended Automotive temperature range.
Doc. No. 1046, Rev. K
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC64
A.C. CHARACTERISTICS
V
CC
= +2.5V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
VCC=2.5V - 5.5V
Min
F
SCL
t
AA
t
BUF(2)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(2)
t
F(2)
t
SU:STO
t
DH
t
WR
t
SP
t
SU;WP
t
HD;WP
Clock Frequency
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission Can
Start
Start Condition Hold Time
Clock Low Period
Clock High Period
50
1300
600
1300
Max
400
900
Units
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Input Suppresssion (SDA, SCL)
WP Setup Time
WP Hold Time
Power-Up Timing
(2)(3)
Symbol
t
PUR
t
PUW
Note:
(1) AC measurement conditions:
RL (connects to V
CC
): 0.3V
CC
to 0.7 V
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
i
D
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
c
s
n
o
i
t
u
n
d
e
0
50
600
600
a
P
300
300
5
50
t
r
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
100
600
600
1300
Min
Typ
Max
100
100
Units
µs
µs
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Doc No. 1046, Rev. K
3
CAT24FC64
FUNCTIONAL DESCRIPTION
The CAT24FC64 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC64 operates as
a Slave device. Both the Master device and Slave device
can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left connected. When
hardwired, up to eight CAT24FC64's may be addressed
on a single bus system. When the pins are left
unconnected, the default values are zero.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tHIGH
tLOW
tR
SDA IN
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
Figure 3. Start/Stop Timing
i
D
c
s
8TH BIT
BYTE n
n
o
tAA
ACK
i
t
u
n
tDH
tWR
tSU:DAT
d
e
a
P
tSU:STO
tBUF
t
r
STOP
CONDITION
START
CONDITION
ADDRESS
SDA
SCL
START BIT
STOP BIT
Doc. No. 1046, Rev. K
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24FC64
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC64 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
as many as eight devices on the same bus. These bits
must compare to their hardwired input pins. The last bit
of the slave address specifies whether a Read or Write
operation is to be performed. When this bit is set to 1, a
Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC64 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC64 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The CAT24FC64 uses the next three bits
as address bits. The address bits A2, A1 and A0 allow
Figure 4. Acknowledge Timing
i
D
DATA OUTPUT
FROM TRANSMITTER
c
s
SCL FROM
MASTER
n
o
START
i
t
1
u
n
The CAT24FC64 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24FC64 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24FC64 will continue to transmit
d
e
8
a
P
t
r
9
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1046, Rev. K
stm32/stm8
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