CY7C1460AV33
CY7C1462AV33
36-Mbit (1 M × 36/2 M × 18)
Pipelined SRAM with NoBL™ Architecture
36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
■
■
Functional Description
The CY7C1460AV33/CY7C1462AV33 are 3.3 V, 1 M × 36/2 M × 18
synchronous pipelined burst SRAMs with No Bus Latency™
(NoBL logic, respectively. They are designed to support
unlimited true back-to-back read/write operations with no wait
states. The CY7C1460AV33/CY7C1462AV33 are equipped with
the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1460AV33/CY7C1462AV33 are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BW
a
–BW
d
for CY7C1460AV33 and BW
a
–BW
b
for
CY7C1462AV33) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Pin compatible and functionally equivalent to ZBT
Supports 250 MHz bus operations with zero wait states
❐
Available speed grades are 250, 200 and 167 MHz
Internally self timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
3.3 V power supply
3.3 V/2.5 V I/O power supply
Fast clock-to-output times
❐
2.6 ns (for 250 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self timed writes
CY7C1460AV33 available in JEDEC-standard Pb-free 100-pin
TQFP and non Pb-free 165-ball FBGA package.
CY7C1462AV33 available in JEDEC-standard Pb-free 100-pin
TQFP.
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
■
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram – CY7C1460AV33
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQ s
DQ P
a
DQ P
b
DQ P
c
DQ P
d
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Cypress Semiconductor Corporation
Document Number: 38-05353 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 5, 2012
CY7C1460AV33
CY7C1462AV33
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Burst Read Accesses .................................................. 7
Single Write Accesses ................................................. 7
Burst Write Accesses .................................................. 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Partial Write Cycle Description ..................................... 10
Partial Write Cycle Description ..................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing Diagram ...................................................... 14
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 15
3.3 V TAP AC Output Load Equivalent ......................... 15
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
TAP DC Electrical Characteristics and
Operating Conditions .................................................. 16
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Neutron Soft Error Immunity ......................................... 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagrams .......................................................... 26
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC Solutions ......................................................... 31
Document Number: 38-05353 Rev. *L
Page 3 of 31
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
