a
FEATURES
Improved Version of AD7541
Full Four-Quadrant Multiplication
12-Bit Linearity (Endpoint)
All Parts Guaranteed Monotonic
TTL/CMOS Compatible
Low Cost
Protection Schottky Diodes Not Required
Low Logic Input Leakage
CMOS
12-Bit Monolithic Multiplying DAC
AD7541A
FUNCTIONAL BLOCK DIAGRAM
10kΩ
V
REF
20kΩ
S1
20kΩ
S2
20kΩ
S3
20kΩ
S12
20kΩ
10kΩ
10kΩ
OUT2
OUT1
10kΩ
R
FEEDBACK
GENERAL DESCRIPTION
The Analog Devices AD7541A is a low cost, high performance
12-bit monolithic multiplying digital-to-analog converter. It is
fabricated using advanced, low noise, thin film on CMOS
technology and is available in a standard 18-lead DIP and in
20-terminal surface mount packages.
The AD7541A is functionally and pin compatible with the in-
dustry standard AD7541 device and offers improved specifica-
tions and performance. The improved design ensures that the
device is latch-up free so no output protection Schottky diodes
are required.
This new device uses laser wafer trimming to provide full 12-bit
endpoint linearity with several new high performance grades.
ORDERING GUIDE
Temperature
Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
1
BIT 1 (MSB)
BIT 2
BIT 3
BIT 12 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO I
OUT1
FOR
ITS DIGITAL INPUT IN A "HIGH" STATE.
PRODUCT HIGHLIGHTS
Compatibility:
The AD7541A can be used as a direct replace-
ment for any AD7541-type device. As with the Analog Devices
AD7541, the digital inputs are TTL/CMOS compatible and
have been designed to have a
±
1
µA
maximum input current
requirement so as not to load the driving circuitry.
Improvements:
The AD7541A offers the following improved
specifications over the AD7541:
1. Gain Error for all grades has been reduced with premium
grade versions having a maximum gain error of
±
3 LSB.
Model
2
AD7541AJN
AD7541AKN
AD7541AJP
AD7541AKP
AD7541AKR
AD7541AAQ
AD7541ABQ
AD7541ASQ
AD7541ATQ
AD7541ASE
AD7541ATE
Relative
Gain
Accuracy
Error
T
MIN
to T
MAX
T
A
= +25 C
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
6 LSB
±
1 LSB
±
6
±
1
±
1
±
6 LSB
±
1 LSB
±
6 LSB
±
1 LSB
±
6 LSB
±
1 LSB
Package
Options
3
N-18
N-18
P-20A
P-20A
R-18
Q-18
Q-18
Q-18
Q-18
E-20A
E-20A
2. Gain Error temperature coefficient has been reduced to
2 ppm/°C typical and 5 ppm/°C maximum.
3. Digital-to-analog charge injection energy for this new device
is typically 20% less than the standard AD7541 part.
4. Latch-up proof.
5. Improvements in laser wafer trimming provides 1/2 LSB max
differential nonlinearity for top grade devices over the operat-
ing temperature range (vs. 1 LSB on older 7541 types).
6. All grades are guaranteed monotonic to 12 bits over the
operating temperature range.
NOTES
1
Analog Devices reserves the right to ship either ceramic (D-18) or cerdip (Q-18)
hermetic packages.
2
To order MIL-STD-883, Class B process parts, add /883B to part number. Contact
local sales office for military data sheet.
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = Small Outline IC.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD7541A–SPECIFICATIONS
(V
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Version
T
A
=
+25 C
All
J, A, S
K, B, T
J, A, S
K, B, T
J, A, S
K, B, T
12
±
1
±
1/2
±
1
±
1/2
±
6
±
3
DD
= +15 V, V
REF
= +10 V; OUT 1 = OUT 2 = GND = 0 V unless otherwise noted)
T
A
=
T
MIN,
T
MAX1
Units
Test Conditions/Comments
12
±
1
±
1/2
±
1
±
1/2
±
8
±
5
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
±
1 LSB =
±0.024%
of Full Scale
±
1/2 LSB =
±
0.012% of Full Scale
All Grades Guaranteed Monotonic
to 12 Bits, T
MIN
to T
MAX
.
Measured Using Internal R
FB
and Includes
Effect of Leakage Current and Gain TC.
Gain Error Can Be Trimmed to Zero.
Typical Value Is 2 ppm/°C.
All Digital Inputs = 0 V.
Gain Temperature Coefficient
2
Gain/ Temperature
Output Leakage Current
OUT1 (Pin 1)
All
J, K
A, B
S, T
J, K
A, B
S, T
All
5
±
5
±
5
±
5
±
5
±
5
±
5
7–18
5
±
10
±
10
±
200
±
10
±
10
±
200
7–18
ppm/°C max
nA max
nA max
nA max
nA max
nA max
nA max
kΩ min/max
OUT2 (Pin 2)
All Digital Inputs = V
DD
.
REFERENCE INPUT
Input Resistance (Pin 17 to GND)
Typical Input Resistance = 11 kΩ.
Typical Input Resistance Temperature
Coefficient = –300 ppm/°C.
DIGITAL INPUTS
V
IH
(Input HIGH Voltage)
V
IL
(Input LOW Voltage)
I
IN
(Input Current)
C
IN
(Input Capacitance)
2
POWER SUPPLY REJECTION
Gain/ V
DD
POWER SUPPLY
V
DD
Range
I
DD
All
All
All
All
All
All
All
2.4
0.8
±
1
8
±
0.01
+5 to +16
2
100
2.4
0.8
±
1
8
±
0.02
+5 to +16
2
500
V min
V max
µA
max
pF max
% per % max
V min/V max
mA max
µA
max
Logic Inputs Are MOS Gates. I
IN
typ (25°C) = 1 nA.
V
IN
= 0 V
V
DD
=
±
5%
Accuracy Is Not Guaranteed Over This Range.
All Digital Inputs V
IL
or V
IH
.
All Digital Inputs 0 V or V
DD
.
AC PERFORMANCE CHARACTERISTICS
These Characteristics are included for Design Guidance only and are not subject to test. V
DD
= +15 V, V
IN
= +10 V except where noted,
OUT1 = 0UT2 = GND = 0 V, Output Amp is AD544 except where noted.
Parameter
PROPAGATION DELAY (From Digital Input
Change to 90% of Final Analog Output)
DIGITAL TO ANALOG GLITCH
IMPULSE
All
MULTIPLYING FEEDTHROUGH ERROR
3
(V
REF
to OUT1)
OUTPUT CURRENT SETTLING TIME
All
All
1000
1.0
0.6
—
—
—
nV-sec typ
mV p-p typ
µs
typ
Version
1
T
A
=
+25 C
T
A
=
T
MIN,
T
MAX1
Units
Test Conditions/Comments
OUT 1 Load = 100
Ω,
C
EXT
= 13 pF.
Digital Inputs = 0 V to V
DD
or V
DD
to 0 V.
V
REF
= 0 V. All digital inputs 0 V to V
DD
or
V
DD
to 0 V.
Measured using Model 50K as output amplifier.
V
REF
=
±
10 V, 10 kHz sine wave.
To 0.01% of full-scale range.
OUT 1 Load = 100
Ω,
C
EXT
= 13 pF.
Digital Inputs = 0 V to V
DD
or V
DD
to 0 V.
Digital Inputs
= V
IH
Digital Inputs
= V
IL
All
100
—
ns typ
OUTPUT CAPACITANCE
C
OUT1
(Pin 1)
C
OUT2
(Pin 2)
C
OUT1
(Pin 1)
C
OUT2
(Pin 2)
All
All
All
All
200
70
70
200
200
70
70
200
pF max
pF max
pF max
pF max
NOTES
1
Temperature range as follows: J, K versions, 0°C to +70°C; A, B versions, –25°C to +85°C; S, T versions, –55°C to +125°C.
2
Guaranteed by design but not production tested.
3
To minimize feedthrough in the ceramic package (Suffix D) the user must ground the metal lid.
Specifications subject to change without notice.
–2–
REV. B
AD7541A
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
V
RFB
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
25 V
Digital Input Voltage to GND . . . . . . . . –0.3 V, V
DD
+ 0.3 V
OUT 1, OUT 2 to GND . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . –25°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7541A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
RELATIVE ACCURACY
OUTPUT LEAKAGE CURRENT
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is expressed in % of full-
scale range or (sub)multiples of 1 LSB.
DIFFERENTIAL NONLINEARITY
Current which appears at OUTI with the DAC loaded to all 0s
or at OUT2 with the DAC loaded to all 1s.
MULTIPLYING FEEDTHROUGH ERROR
AC error due to capacitive feedthrough from V
REF
terminal to
OUT1 with DAC loaded to all 0s.
OUTPUT CURRENT SETTLING TIME
Differential nonlinearity is the difference between the
measured
change and the
ideal
l LSB change between any two adjacent
codes. A specified differential nonlinearity of
±1
LSB max over
the operating temperature range insures monotonicity.
GAIN ERROR
Time required for the output function of the DAC to settle to
within 1/2 LSB for a given digital input stimulus, i.e., 0 to full
scale.
PROPAGATION DELAY
Gain error is a measure of the output error between an ideal
DAC and the actual device output. For the AD7541A, ideal
maximum output is
4095
–
4096
(V
REF
).
Gain error is adjustable to zero using external trims as shown in
Figures 4, 5 and 6.
This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG CHARGE INJECTION (QDA)
This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with V
REF
= GND and a Model 50K as the
output op amp, C1 (phase compensation) = 0 pF.
PIN CONFIGURATIONS
DIP/SOIC
OUT 2
OUT 1
NC
OUT1 1
OUT2 2
GND 3
BIT 1 (MSB) 4
BIT 2 5
18 R
FEEDBACK
17 V
REF
IN
16 V
DD
(+)
GND 4
BIT 1 (MSB) 5
BIT 2 6
BIT 3 7
BIT 4 8
9 10 11 12 13
BIT 7
BIT 5
BIT 6
NC = NO CONNECT
BIT 8
NC
NC = NO CONNECT
LCCC
OUT 2
OUT 1
V
REF
R
FB
NC
PLCC
V
REF
18 V
DD
17 BIT 12 (LSB)
16 BIT 11
15 BIT 10
14 BIT 9
9
BIT 5
10 11 12 13
BIT 6
BIT 7
BIT 8
NC
R
FB
3
2
1 20 19
18 V
DD
GND 4
BIT 1 (MSB) 5
BIT 2 6
BIT 3 7
BIT 4 8
3
2
1
20 19
PIN 1
IDENTIFIER
AD7541A
15 BIT 12 (LSB)
AD7541A
TOP VIEW
(Not to Scale)
17 BIT 12 (LSB)
16 BIT 11
15 BIT 10
14 BIT 9
TOP VIEW 14 BIT 11
(Not to Scale)
BIT 3 6
13 BIT 10
BIT 4 7
BIT 5 8
BIT 6 9
12 BIT 9
11 BIT 8
10 BIT 7
AD7541A
TOP VIEW
(Not to Scale)
REV. B
–3–
AD7541A
GENERAL CIRCUIT INFORMATION
The simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
10kΩ
V
REF
20kΩ
S1
20kΩ
S2
20kΩ
S3
20kΩ
S12
20kΩ
10kΩ
10kΩ
APPLICATIONS
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. With a dc
reference voltage or current (positive or negative polarity) ap-
plied at Pin 17, the circuit is a unipolar D/A converter. With an
ac reference voltage or current, the circuit provides 2-quadrant
multiplication (digitally controlled attenuation). The input/
output relationship is shown in Table II.
R1 provides full-scale trim capability [i.e., load the DAC register
to 1111 1111 1111, adjust R1 for V
OUT
= –V
REF
(4095/4096)].
Alternatively, Full Scale can be adjusted by omitting R1 and R2
and trimming the reference voltage magnitude.
C1 phase compensation (10 pF to 25 pF) may be required for
stability when using high speed amplifiers. (C1 is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUT1).
Amplifier A1 should be selected or trimmed to provide V
OS
≤
10% of the voltage resolution at V
OUT
. Additionally, the ampli-
fier should exhibit a bias current which is low over the tempera-
ture range of interest (bias current causes output offset at V
OUT
equal to I
B
times the DAC feedback resistance, nominally 11 kΩ).
The AD544L is a high speed implanted FET input op amp with
low factory-trimmed V
OS
.
V
DD
R2
*
18
R
FB
OUT1 1
OUT2
PINS 4–15
DGND
3
2
AD544L
(SEE TEXT)
ANALOG
COMMON
C1
33pF
V
OUT
OUT2
OUT1
10kΩ
R
FEEDBACK
BIT 1 (MSB)
BIT 2
BIT 3
BIT 12 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO I
OUT1
FOR
ITS DIGITAL INPUT IN A "HIGH" STATE.
Figure 1. Functional Diagram (Inputs HIGH)
The input resistance at V
REF
(Figure 1) is always equal to R
LDR
(R
LDR
is the R/2R ladder characteristic resistance and is equal to
value “R”). Since R
IN
at the V
REF
pin is constant, the reference
terminal can be driven by a reference voltage or a reference
current, ac or dc, of positive or negative polarity. (If a current
source is used, a low temperature coefficient external R
FB
is
recommended to define scale factor.)
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs LOW and all digital
inputs HIGH are shown in Figures 2 and 3. In Figure 2 with all
digital inputs LOW, the reference current is switched to OUT2.
The current source I
LEAKAGE
is composed of surface and junc-
tion leakages to the substrate, while the I/
4096
current source
represents a constant 1-bit current drain through the termina-
tion resistor on the R-2R ladder. The ON capacitance of the
output N-channel switch is 200 pF, as shown on the OUT2
terminal. The OFF switch capacitance is 70 pF, as shown on
the OUT1 terminal. Analysis of the circuit for all digital inputs
HIGH, as shown in Figure 3 is similar to Figure 2; however, the
ON switches are now on terminal OUT1, hence the 200 pF at
that terminal.
RFB
R
OUT1
I
LEAKAGE
R
V
REF
I
REF
I
/4096
I
LEAKAGE
200pF
15kΩ
OUT2
70pF
16
V
IN
R1
*
V
DD
17 V
REF
AD7541A
BIT 1 – BIT 12
DIGITAL
GROUND
*
REFER TO TABLE 1
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades
Trim
Resistor
R1
R2
JN/AQ/SD
100
Ω
47
Ω
KN/BQ/TD
100
Ω
33
Ω
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC
MSB
LSB
Figure 2. DAC Equivalent Circuit All Digital Inputs LOW
RFB
R
V
REF
I
REF
I
/4096
I
LEAKAGE
200pF
15kΩ
R
OUT1
Analog Output, V
OUT
4095
–V
IN
4096
2048
–V
IN
4096
= –1/2 V
IN
1
–V
IN
4096
0 Volts
REV. B
1111
1111
1111
1000
OUT2
70pF
0000
0000
I
LEAKAGE
0000
Figure 3. DAC Equivalent Circuit All Digital Inputs HIGH
0000
0000
0001
0000
0000
–4–
AD7541A
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
Figure 5 and Table III illustrate the circuitry and code relation-
ship for bipolar operation. With a dc reference (positive or nega-
tive polarity) the circuit provides offset binary operation. With
an ac reference the circuit provides full 4-quadrant multiplication.
With the DAC loaded to 1000 0000 0000, adjust R1 for
V
OUT
= 0 V (alternatively, one can omit R1 and R2 and adjust
the ratio of R3 to R4 for V
OUT
= 0 V). Full-scale trimming can
be accomplished by adjusting the amplitude of V
REF
or by vary-
ing the value of R5.
As in unipolar operation, A1 must be chosen for low V
OS
and
low I
B
. R3, R4 and R5 must be selected for matching and track-
ing. Mismatch of 2R3 to R4 causes both offset and full-scale
error. Mismatch of R5 to R4 or 2R3 causes full-scale error. C1
phase compensation (10 pF to 50 pF) may be required for sta-
bility, depending on amplifier used.
V
DD
R2
*
C1
33pF
OUT1 1
A1
AD544L
R6
5kΩ
10%
ANALOG
COMMON
BIT 1 – BIT 12
DIGITAL
GROUND
A2
V
OUT
AD544J
OUT2 2
GND
3
R3
10kΩ
R4
20kΩ
R5
20kΩ
Figure 6 and Table IV show an alternative method of achieving
bipolar output. The circuit operates with sign plus magnitude
code and has the advantage of giving 12-bit resolution in each
quadrant, compared with 11-bit resolution per quadrant for the
circuit of Figure 5. The AD7592 is a fully protected CMOS
changeover switch with data latches. R4 and R5 should match
each other to 0.01% to maintain the accuracy of the D/A con-
verter. Mismatch between R4 and R5 introduces a gain error.
V
DD
R2
*
C1
33pF
OUT1 1
A1
AD544L
ANALOG
COMMON
OUT2 2
GND
3
R4
20kΩ
R3
10kΩ
10%
1/2 AD7592JN
DIGITAL
GROUND
R5
20kΩ
V
OUT
A2
AD544J
16
V
DD
V
IN
R1
*
17 V
REF
18
R
FB
AD7541A
PINS 4–15
SIGN BIT
BIT 1 – BIT 12
*
FOR VALUES OF R1 AND R2
SEE TABLE 1.
Figure 6. 12-Bit Plus Sign Magnitude Operation
Table IV. 12-Bit Plus Sign Magnitude Code Table for Circuit
of Figure 6
16
V
DD
V
IN
R1
*
17 V
REF
18
R
FB
AD7541A
PINS 4–15
Sign
Bit
Binary Number in DAC
MSB
LSB
Analog Output, V
OUT
4095
+V
IN
×
4096
0 Volts
0 Volts
4095
–V
IN
×
4096
*
FOR VALUES OF R1 AND R2
SEE TABLE 1.
0
Figure 5. Bipolar Operation (4-Quadrant Multiplication)
1111 1111 1111
0000 0000 0000
0000 0000 0000
1111 1111 1111
0
Table III. Bipolar Code Table for Offset Binary Circuit of
Figure 5
1
1
Binary Number in DAC
MSB
LSB
Analog Output, V
OUT
Note: Sign bit of “0” connects R3 to GND.
1111
1111
1111
2047
+V
IN
2048
1
+V
IN
2048
0 Volts
1
–V
IN
2048
2048
–V
IN
2048
1000
1000
0111
0000
0000
1111
0001
0000
1111
0000
0000
0000
REV. B
–5–
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