Si5326
A
N Y
F
R E Q UE N C Y
P
R E C I S I O N
C
L O C K
M
U L T I P L I E R
/ J
I T T E R
A
TTENUATOR
Features
Generates any frequency from 2 kHz
to 945 MHz and select frequencies to
1.4 GHz from an input frequency of
2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter
generation as low as 0.3 ps rms
(50 kHz–80 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter
specifications
Dual clock inputs with manual or
automatically controlled hitless
switching (LVPECL, LVDS, CML,
CMOS)
Dual clock outputs with selectable
signal format
Support for ITU G.709 and custom
FEC ratios (255/238, 255/237,
255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase
adjustment
I
2
C or SPI programmable
On-chip voltage regulator for
1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%
operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
Ordering Information:
See page 65.
Pin Assignments
CKOUT1–
CKOUT2+
CMODE
CKOUT2–
SONET/SDH OC-48/OC-192/STM-
16/STM-64 line cards
ITU G.709 and custom FEC line
cards
GbE/10GbE, 1/2/4/8/10G Fibre
Channel line cards
GbE/10GbE Synchronous Ethernet
Optical modules
Wireless basestations
Data converter clocking
xDSL
PDH clock synthesis
Test and measurement
Broadcast video
GND
36 35 34 33 32 31 30 29 28
RST
NC
INT_C1B
C2B
VDD
XA
XB
GND
NC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
NC
CKIN1+
RATE0
RATE1
CKIN2+
CKIN1–
CKIN2–
VDD
LOL
27 SDI
26 A2_SS
25 A1
CKOUT1+
24 A0
23 SDA_SDO
22 SCL
21 CS_CA
20 INC
19 DEC
Applications
VDD
NC
GND
Pad
Description
The Si5326 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to
945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down
separately from a common source. The Si5326 can also use its crystal oscillator
as a clock source for frequency synthesis. The device provides virtually any
frequency translation combination across this operating range. The Si5326 input
clock frequency and clock multiplication ratio are programmable through an I
2
C or
SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation
DSPLL
®
technology, which provides frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating from a
single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock
multiplication and jitter attenuation in high performance timing applications.
Rev. 1.0 9/10
Copyright © 2010 by Silicon Laboratories
NC
Si5326
Si5326
T
ABLE O F
C
ONTENTS
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Pin Descriptions: Si5326 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11. Si5326 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Rev. 1.0
3
Si5326
Table 2. DC Characteristics
(V
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Supply Current
1
Symbol
I
DD
Test Condition
LVPECL Format
622.08 MHz Out
Both CKOUTs Enabled
LVPECL Format
622.08 MHz Out
1 CKOUT Enabled
CMOS Format
19.44 MHz Out
Both CKOUTs Enabled
CMOS Format
19.44 MHz Out
1 CKOUT Enabled
Disable Mode
Min
—
Typ
251
Max
279
Unit
mA
—
217
243
mA
—
204
234
mA
—
194
220
mA
—
165
—
mA
CKINn Input Pins
2
Input Common Mode
Voltage (Input Thresh-
old Voltage)
V
ICM
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Input Resistance
Single-Ended Input
Voltage Swing
(See Absolute Specs)
CKN
RIN
V
ISE
Single-ended
f
CKIN
< 212.5 MHz
See Figure 1.
f
CKIN
> 212.5 MHz
See Figure 1.
V
ID
f
CKIN
< 212.5 MHz
See Figure 1.
fCKIN > 212.5 MHz
See Figure 1.
0.9
1
1.1
20
0.2
0.25
0.2
0.25
—
—
—
40
—
—
—
—
1.4
1.7
1.95
60
—
—
—
—
V
V
V
kΩ
V
PP
V
PP
V
PP
V
PP
Differential Input
Voltage Swing
(See Absolute Specs)
Output Clocks (CKOUTn)
3
Common Mode
CKO
VCM
LVPECL 100
load line-
to-line
V
DD
–
1.42
—
V
DD
–1.25
V
Notes:
1.
Current draw is independent of supply voltage
2.
No under- or overshoot is allowed.
3.
LVPECL outputs require nominal V
DD
≥
2.5 V.
4.
This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Rev. 1.0
5
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