ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8731-01 is a low voltage, low skew,
1-to-11 Differential-to-3.3V LVPECL Clock Multiplier/Zero
Delay Buffer. With output frequencies up to 700MHz the
ICS8731-01 is targeted at high performance clock
applications. Along with a fully integrated PLL the ICS8731-
01 contains frequency configurable, differential outputs
and external feedback inputs for multiplying clock
frequencies and regenerating clocks with “zero delay”.
Frequency multiplication is achieved by utilizing the
separate feedback and clock output dividers. The value of
the multiplier is determined by the ratio of the feedback
divider, M, to the output divider,N. For multiplier values
greater than 1, M must be greater than N. For multiplier
values less than 1,M must be less than N. The zero delay
mode is achieved with M and N at equal values. The divide
values of the clock and feedback outputs are controlled by
the DIV_SEL0:2 and FB_SEL0:1 inputs, respectively. The
ICS8731-01 accepts any differential signal and translates
it to differential 3.3V LVPECL output levels.
F
EATURES
•
Eleven differential 3.3V LVPECL outputs
•
Differential reference clock input pair
•
REF_CLK, nREF_CLK pair can accept the following
differential input levels: LVPECL, LVDS, LVHSTL, SSTL,
HCSL
•
Maximum output frequency: 700MHz
•
Maximum reference clock input frequency: 200MHz
•
VCO range: 250MHz - 700MHz
•
Accepts any single-ended input signal with a resistor bias
on nCLK input
•
External feedback for zero delay capabilitiy
•
Output skew: 70ps (maximum)
•
Cycle-to-cycle jitter: 65ps (maximum)
•
Full 3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
PLL_SEL
V
CCO
Q4
nQ4
Q5
nQ5
V
EE
Q6
nQ6
Q7
nQ7
V
CCO
DIV_SEL0
DIV_SEL1
DIV_SEL2
÷1
÷2
÷4
÷6
÷8
100
000
001
010
011
MR
V
CCO
Q8
nQ8
Q9
Q0:Q9
nQ9
nQ0:nQ9
V
EE
Q10/FB_OUT
nQ10/nFB_OUT
V
CCO
FB_IN
Q10/FB_OUT
nFB_IN
nQ10/nFB_OUT
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
V
CCO
nQ3
Q3
nQ2
Q2
V
EE
nQ1
Q1
nQ0
Q0
V
CCO
nc
0
REF_CLK
nREF_CLK
FB_IN
nFB_IN
1
ICS8731-01
PLL
÷2
÷4
÷6
÷8
00
01
10
11
PLL_SEL
MR
FB_SEL1
FB_SEL0
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
DIV_SEL2
DIV_SEL1
DIV_SEL0
V
CCA
V
EE
REF_CLK
nREF_CLK
FB_SEL1
FB_SEL0
V
CC
V
EE
nc
8731CY-01
www.idt.com
1
REV. B JULY 27, 2010
ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 10,
26, 36,
38, 48
3, 4,
5, 6
7, 14, 20,
31, 43
8,
9
11, 12
15
16
17
18
19
21
22
23
24
13, 25
27, 28
29, 30
32, 33,
34, 35
37
Name
MR
Input
Type
Description
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs, Qx, to go low and the inver ted outputs
Pulldown
nQx to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
Output supply pins.
Differential output pairs.
Negative supply pins.
Differential clock outputs.
Feedback input to phase detector for generating clocks with
"zero delay".
Core supply pin.
Determines output divider for Q10/FB outputs (see Table 3).
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider for Q10/FB outputs (see Table 3).
Pulldown
LVCMOS / LVTTL interface levels.
Pullup Inver ting differential clock input.
Pulldown
Pulldown Non-inver ting differential clock input.
Analog supply pin.
Determines output divider values in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider values in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider values in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
No connect.
Differential output pairs.
Differential output pairs.
Pullup
Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects
PLL. LVCMOS / LVTTL interface levels.
V
CCO
Q8, nQ8,
Q9, nQ9
V
EE
Q10/FB_OUT,
nQ10/nFB_OUT
FB_IN, nFB_IN
V
CC
FB_SEL0
FB_SEL1
nREF_CLK
REF_CLK
V
CCA
DIV_SEL0,
DIV_SEL1
DIV_SEL2
nc
Q0, nQ0,
Q1, nQ1
Q2, nQ2,
Q3, nQ3
PLL_SEL
Power
Output
Power
Output
Input
Power
Input
Input
Input
Input
Power
Input
Input
Input
Unused
Output
Output
Input
39, 40,
Q4, nQ4,
Differential output pairs.
Output
41, 42
Q5, nQ5
44, 45,
Q6, nQ6,
Output
Differential output pairs.
46, 47
Q7, nQ7
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
8731CY-01
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
www.idt.com
2
REV. B JULY 27, 2010
ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
FOR
Q0:Q9 O
UTPUTS
Outputs
DIV_SEL1
X
0
0
0
1
1
0
0
0
1
1
DIV_SEL0
X
0
0
1
0
1
0
0
1
0
1
Q0:Q9, nQ0:nQ9
Low
fVCO/1
fVCO/2
fVCO/4
fVCO/6
fVCO/8
fREF_CLK/1
fREF_CLK/2
fREF_CLK/4
fREF_CLK/6
fREF_CLK/8
Inputs
MR
1
0
0
0
0
0
0
0
0
0
0
PLL_SEL
X
1
1
1
1
1
0
0
0
0
0
DIV_SEL2
X
1
0
0
0
0
1
0
0
0
0
T
ABLE
3B. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
FOR
Q10/FB
Outputs
FB_SEL1
X
0
0
1
1
0
0
1
1
FB_SEL0
X
0
1
0
1
0
1
0
1
Q10/FB, nQ10/FB
Low
fVCO/2
fVCO/4
fVCO/6
fVCO/8
fREF_CLK/2
fREF_CLK/4
fREF_CLK/6
fREF_CLK/8
Inputs
MR
1
0
0
0
0
0
0
0
0
PLL_SEL
X
1
1
1
1
0
0
0
0
T
ABLE
3C. Q
X
O
UTPUT
F
REQUENCY
W
/FB_IN
= Q10/FB
Inputs
fVCO
REF_CLK (MHz)
Minimum
125
62.5
41.67
Maximum
200 (NOTE 2)
175
116.67
87.5
(NOTE 1)
fREF_CLK x 2
fREF_CLK x 4
fREF_CLK x 6
fREF_CLK x 8
FB_IN
Q10/FB
Q10/FB
Q10/FB
FB_SEL1
0
0
1
FB_SEL0
0
1
0
Q10/FB
Output Divider Mode
÷2
÷4
÷6
Q10/FB
1
1
31.25
÷8
NOTE 1: VCO frequency range is 250MHz to 700MHz.
NOTE 2: The maximum input frequency that the phase defector can accept is 200MHz.
8731CY-01
www.idt.com
3
REV. B JULY 27, 2010
ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
195
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
Input High Voltage
PLL_SEL, DIV_SEL0,
DIV_SEL1, DIV_SEL2,
FB_SEL0, FB_SEL1, MR
PLL_SEL, DIV_SEL0,
DIV_SEL1, DIV_SEL2,
FB_SEL0, FB_SEL1, MR
DIV_SEL0, DIV_SEL1,
DIV_SEL2, MR,
FB_SEL0, FB_SEL1
PLL_SEL
DIV_SEL0, DIV_SEL1,
DIV_SEL2, MR,
FB_SEL0, FB_SEL1
PLL_SEL
Test Conditions
Minimum Typical
2
Maximum
V
CC
+ 0.3
Units
V
V
IL
Input Low Voltage
-0.3
0.8
V
I
IH
Input High Current
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
-150
150
5
µA
µA
µA
µA
I
IL
Input Low Current
8731CY-01
www.idt.com
4
REV. B JULY 27, 2010
ICS8731-01
L
OW
S
KEW
, 1-
TO
-11 D
IFFERENTIAL
-
TO
-3.3V LVPECL
C
LOCK
M
ULTIPLIER
/ Z
ERO
D
ELAY
B
UFFER
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
REF_CLK, FB_IN
nREF_CLK, nFB_IN
REF_CLK, FB_IN
nREF_CLK, nFB_IN
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.15
1. 3
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
V
EE
+ 0.5
V
CC
- 0.85
NOTE 1: For single ended applications, the maximum input voltage for REF_CLK, nREF_CLK and FB_IN, nFB_IN
is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
5. PLL I
NPUT
R
EFERENCE
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
REF
Parameter
Input Reference Frequency
Test Conditions
Minimum
Typical
Maximum
200
Units
MHz
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter ; NOTE 4
Test Conditions
PLL_SEL = 0V, ƒ
≤
450MHz
PLL_SEL = 3.3V,
DIV_SEL[2:0] = 000,
FB_SEL[1:0] = 00
Minimum
4.0
50
Typical
Maximum
700
5.5
150
70
65
Units
MHz
ns
ps
ps
ps
ms
ps
%
t
(Ø)
t
sk(o)
t
jit(cc)
PLL Lock Time
1
t
L
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
300
700
odc
Output Duty Cycle
IJ 300MHz
45
55
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
www.idt.com
5
8731CY-01
REV. B JULY 27, 2010
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