Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> 82442FX

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82442FX: 产品描述Microprocessor Circuit, CMOS, PQFP208, PLASTIC, QFP-208; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小406KB，共69页; 制造商Intel(英特尔); 官网地址http://www.intel.com/

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82442FX概述

Microprocessor Circuit, CMOS, PQFP208, PLASTIC, QFP-208

82442FX规格参数

参数名称	属性值
厂商名称	Intel(英特尔)
零件包装代码	QFP
包装说明	PLASTIC, QFP-208
针数	208
Reach Compliance Code	compliant
JESD-30 代码	S-PQFP-G208
长度	28 mm
端子数量	208
封装主体材料	PLASTIC/EPOXY
封装代码	FQFP
封装形状	SQUARE
封装形式	FLATPACK, FINE PITCH
认证状态	Not Qualified
座面最大高度	4.25 mm
表面贴装	YES
技术	CMOS
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
宽度	28 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR CIRCUIT

文档解析

Intel 440FX PCIset 的系统地址映射涉及将系统内存和I/O空间分配给各种硬件组件，以确保它们能够正确地进行数据交换和通信。以下是该系统地址映射的工作原理：

内存地址范围：系统内存被分为几个区域，包括DOS兼容性区域（0-1MB），扩展ISA内存（1MB-16MB），扩展内存区域（16MB-4GB），以及由36位寻址支持的扩展Pentium Pro处理器内存（4GB-64GB）。
DOS兼容性内存：这个区域包括BIOS区域（0-640KB），用于存放系统BIOS和其他基本输入输出系统（BIOS）相关的程序。还包括一个可选的固定内存空洞（512KB-640KB），可以映射到PCI或主内存。
系统管理模式（SMM）内存范围：当启用SMM时，内存地址范围A0000h-BFFFFh被用作SMM RAM。这允许在系统管理模式下访问特定的内存区域。
内存映射：内存被映射为连续的地址空间，允许CPU和其他系统组件访问主内存。这包括DRAM控制器管理的内存，以及通过PCI总线访问的内存。
I/O地址空间：I/O设备通过特定的I/O端口地址进行访问。440FX PCIset支持将I/O访问转发到PCI总线，但某些I/O地址（如配置地址和数据寄存器）是保留给特定用途的。
内存和I/O的属性：内存和I/O空间可以通过编程属性来控制，例如是否可缓存、是否可执行等。这些属性通过内存类型范围寄存器（MTRRs）和其他控制寄存器进行设置。
固定和可编程的内存区域：某些内存区域是固定的，如BIOS区域，而其他区域可以通过编程来定义其大小和属性，以适应不同的系统需求。
内存空洞：在某些配置中，可能会创建内存空洞，这些区域虽然物理上存在内存，但在系统地址映射中不直接映射，而是转发到PCI总线，用于特定的硬件设备。

通过这种地址映射策略，Intel 440FX PCIset 能够支持复杂的系统配置，包括多个处理器、大量内存和各种I/O设备，同时确保它们之间的有效通信。

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PRELIMINARY

INTEL 440FX PCISET

82441FX PCI AND MEMORY CONTROLLER

(PMC) AND 82442FX DATA BUS

ACCELERATOR (DBX)

Supports the Pentium

Pro Processors

at Bus Frequencies Up To 66 Mhz



Supports 32-Bit Addressing



Optimized in-Order and Request

Queue



Full Symmetric Multi-Processor

(SMP) Protocol for up to Two

Processors



Dynamic Deferred Transaction

Support



GTL+ Compliant Host Bus



Supports USWC Cycles

Integrated DRAM Controller



8 MB to 1 GB Main Memory



64/72-Bit Non-Interleaved Path to

Memory



FPM (Fast Page Mode), EDO

(Extended Data Out -Page Mode),

BEDO (Extended Data Out -Burst

Mode) DRAMs Providing x-222 to

x-4-4-4 Burst Capability



Support for Auto Detection of

Memory Type: BEDO, EDO or FPM



8 RAS Lines Available



Support for 4-, 16- and 64-Mb DRAM

Devices



Support for Symmetrical and

Asymmetrical DRAM Addressing



Configurable Support for ECC or

Parity



ECC with Single Bit Error

Correction and Multiple Bit Error

Detection



Read-Around-Write Support for

Host and PCI DRAM Read Accesses



Supports 3.3V or 5V DRAMs

PCI Bus Interface



PCI Rev. 2.1, 5V Interface Compliant



Greater than 100 MBps Data

Streaming for PCI to DRAM

Accesses Enables Native Signal

Processing (NSP) on Systems

Designed With the Pentium Pro

Processor



Integrated Arbiter With Multi-

Transaction PCI Arbitration

Accelerator Hooks



5 PCI Bus Masters are Supported in

Addition to the Host and PCI-to-ISA

I/O Bridge



Delayed Transaction Support



PCI Parity Checking and Generation

Support



Supports Concurrent Pentium Pro

and PCI Transactions to Main

Memory

Data Buffering For Increased

Performance



Extensive CPU-to-DRAM and PCI-

to-DRAM Write Data Buffering



Write Combining Support for CPU-

to-PCI Burst Writes

System Management Mode (SMM)

Compliant

208-Pin PQFP PCI Bridge/ Memory

Controller (PMC), 208-Pin PQFP for the

440FX PCIset Data Bus Accelerator

(DBX)

The Intel 440FX PCIset provides a highly integrated solution for systems based on one or two Pentium

Pro

processors. The 440FX PCIset consists of the 82441FX PCI and Memory Controller (PMC), the 82442FX Data

Bus Accelerator (DBX), and the 82371SB PCI I/O IDE Xcelerator (PIIX3). The PMC and DBX provide a two-chip

host-to-PCI bridge including the DRAM control function, the PCI interface, and the PCI arbiter function. The

440FX PCIset supports EDO, FPM, and BEDO DRAM technologies. The DRAM controller provides support for

up to eight rows of memory and optional DRAM error detection/correction or parity. The 440FX PCIset contains

extensive buffering between all interfaces for high system data throughput and concurrent operations.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights

is granted by this document or by the sale of Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a

particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The Intel 440FX

PCIset may contain design defects or errors known as errata. Current characterized errata are available on request. Third-party brands and names are the property

of their respective owners.

May 1996

Order Number: 290549-001

82441FX (PMC) AND 82442FX (DBX)

CONTENTS

PAGE

1.0. OVERVIEW ......................................................................................................................................................6

2.0. SIGNAL DESCRIPTION ..................................................................................................................................8

2.1. PMC Signals .................................................................................................................................................9

2.1.1. HOST INTERFACE (PMC)....................................................................................................................9

2.1.2. DRAM INTERFACE (PMC) .................................................................................................................10

2.1.3. PCI INTERFACE (PMC)......................................................................................................................11

2.1.4. PCI SIDEBAND INTERFACE (PMC) ..................................................................................................12

2.1.5. DBX INTERFACE (PMC) ....................................................................................................................13

2.1.6. CLOCKS (PMC)...................................................................................................................................13

2.1.7. MISCELLANEOUS (PMC)...................................................................................................................13

2.1.8. POWER UP STRAP OPTIONS (PMC) ...............................................................................................14

2.2. DBX Signals................................................................................................................................................15

2.2.1. DRAM INTERFACE SIGNALS (DBX).................................................................................................15

2.2.2. PMC INTERFACE SIGNALS (DBX)....................................................................................................15

2.2.3. HOST INTERFACE SIGNALS (DBX) .................................................................................................15

2.2.4. MISCELLANEOUS (DBX) ...................................................................................................................16

2.2.5. POWER UP STRAP OPTIONS (DBX)................................................................................................16

3.0. REGISTER DESCRIPTION ...........................................................................................................................17

3.1. I/O Mapped Registers .................................................................................................................................17

3.1.1. CONFADDCONFIGURATION ADDRESS REGISTER ..................................................................18

3.1.2. CONFDATACONFIGURATION DATA REGISTER ........................................................................18

3.2. PCI Configuration Space Mapped Registers ..............................................................................................19

3.2.1. PCI CONFIGURATION ACCESS .......................................................................................................19

3.2.2. VIDVENDOR IDENTIFICATION REGISTER..................................................................................21

3.2.3. DIDDEVICE IDENTIFICATION REGISTER....................................................................................21

3.2.4. PCICMDPCI COMMAND REGISTER .............................................................................................21

3.2.5. PCISTSPCI STATUS REGISTER ...................................................................................................22

3.2.6. RIDREVISION IDENTIFICATION REGISTER................................................................................23

3.2.7. CLASSCCLASS CODE REGISTER................................................................................................23

3.2.8. MLTMASTER LATENCY TIMER REGISTER .................................................................................24

3.2.9. HEADTHEADER TYPE REGISTER................................................................................................24

3.2.10. BISTBIST REGISTER....................................................................................................................24

3.2.11. PMCCFGPMC CONFIGURATION REGISTER ............................................................................25

3.2.12. DETURBODETURBO COUNTER REGISTER.............................................................................26

3.2.13. DBCDBX BUFFER CONTROL......................................................................................................26

3.2.14. AXCAUXILIARY CONTROL REGISTER ......................................................................................27

3.2.15. DRT

DRAM

ROW TYPE REGISTER ............................................................................................28

3.2.16. DRAMCDRAM CONTROL REGISTER.........................................................................................28

3.2.17. DRAMT

DRAM

TIMING REGISTER .............................................................................................29

3.2.18. PAMPROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0])..........................................30

3.2.19. DRB[0:7]

DRAM

ROW BOUNDARY REGISTERS .......................................................................32

PRELIMINARY

82441FX (PMC) AND 82442FX (DBX)

3.2.20. FDHCFIXED DRAM HOLE CONTROL REGISTER ....................................................................33

3.2.21. MTTMULTI-TRANSACTION TIMER REGISTER..........................................................................34

3.2.22. CLTCPU LATENCY TIMER REGISTER .......................................................................................34

3.2.23. SMRAMSYSTEM MANAGEMENT RAM CONTROL REGISTER ................................................35

3.2.24. ERRCMDERROR COMMAND REGISTER ..................................................................................36

3.2.25. ERRSTSERROR STATUS REGISTER ........................................................................................37

3.2.26. TRCTURBO RESET CONTROL REGISTER ...............................................................................38

4.0. FUNCTIONAL DESCRIPTION ......................................................................................................................39

4.1. System Address Map..................................................................................................................................39

4.1.1. MEMORY ADDRESS RANGES..........................................................................................................39

4.1.1.1. Compatibility Area .........................................................................................................................40

4.1.1.2. Extended Memory Area ................................................................................................................41

4.1.2. SYSTEM MANAGEMENT MODE (SMM) MEMORY RANGE............................................................42

4.1.3. MEMORY SHADOWING.....................................................................................................................42

4.1.4. I/O ADDRESS SPACE ........................................................................................................................42

4.2. Host Interface..............................................................................................................................................42

4.3. DRAM Interface ..........................................................................................................................................43

4.3.1. DRAM POPULATION RULES.............................................................................................................43

4.3.2. AUTO-DETECTION.............................................................................................................................45

4.3.3. DRAM ADDRESS TRANSLATION AND DECODING .......................................................................46

4.3.4. PSEUDO-ALGORITHM FOR DYNAMIC MEMORY SIZING .............................................................47

4.3.5. DATA INTEGRITY SUPPORT ............................................................................................................48

4.3.5.1. Software Requirements.................................................................................................................48

4.3.5.2. Parity Detection.............................................................................................................................48

4.3.5.3. Error Detection and correction ......................................................................................................49

4.3.5.4. ECC/Parity Test Mode ..................................................................................................................52

4.4. PCI Bus Arbitration .....................................................................................................................................53

4.5. System Clocking and Reset........................................................................................................................54

4.5.1. HOST FREQUENCY SUPPORT ........................................................................................................54

4.5.2. CLOCK GENERATION AND DISTRIBUTION....................................................................................54

4.5.3. SYSTEM RESET .................................................................................................................................54

4.5.3.1. Hard Reset ....................................................................................................................................55

4.5.3.2. Soft Reset .....................................................................................................................................57

4.5.3.3. CPU BIST......................................................................................................................................57

5.0. PINOUT AND PACKAGE SPECIFICATIONS ..............................................................................................58

5.1. PMC Pinout Information ..............................................................................................................................58

5.2. DBX Pinout Information...............................................................................................................................62

5.3. PMC & DBX Package Specifications..........................................................................................................66

6.0. TESTABILITY.................................................................................................................................................67

6.1. 82441FX (PMC) Test Modes ......................................................................................................................67

6.2. DBX Test Mode...........................................................................................................................................68

PRELIMINARY

82442FX相似产品对比

	82442FX	82441FX
描述	Microprocessor Circuit, CMOS, PQFP208, PLASTIC, QFP-208	PCI Bus Controller, CMOS, PQFP208, PLASTIC, QFP-208
厂商名称	Intel(英特尔)	Intel(英特尔)
零件包装代码	QFP	QFP
包装说明	PLASTIC, QFP-208	FQFP,
针数	208	208
Reach Compliance Code	compliant	compliant
JESD-30 代码	S-PQFP-G208	S-PQFP-G208
长度	28 mm	28 mm
端子数量	208	208
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	FQFP	FQFP
封装形状	SQUARE	SQUARE
封装形式	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH
认证状态	Not Qualified	Not Qualified
座面最大高度	4.25 mm	4.25 mm
表面贴装	YES	YES
技术	CMOS	CMOS
端子形式	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm
端子位置	QUAD	QUAD
宽度	28 mm	28 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR CIRCUIT	BUS CONTROLLER, PCI

82442FX

82442FX概述

82442FX规格参数

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82442FX相似产品对比

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