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AUGUST 1996
DS4585 - 1.6
VP7610
COLOUR DIGITAL VIDEO CAMERA DECODER IC
The VP7610 iCamHost™ Processor chip can decode
the signals from a variety of iVision™ compatible digital video
cameras (such as Silicon Vision’s iCam™) and process them
for use in a host computer system. Digital cameras can offer
real cost and performance gains in applications which require
a digital video input, and iVision technology realises both
these benefits. In a typical analog camera the digitised
output from the CCD imager is normally encoded into an
analog composite video signal which then has to be re-
digitised at the input to the host system. By employing the
iVision approach the output from the camera is maintained as
a digital signal, but in a format which allows for a low cost 9-
wire connection to the host. Eliminating the unnecessary
conversion to an analog signal and back again not only saves
cost, but also avoids any possible degradation of image
quality. Other benefits include direct control of the camera
from the host and the ability to power the camera from the
host system so saving the cost of a separate power supply.
The VP7610 supports two software selectable CamPort™
interface ports, either of which can receive the digital video
from an iVision™ compatible digital video camera. The
output is a standard colour digital video signal, similar to
standard composite analog-digital decoder chips such as the
Philips SAA7110 and SAA7111. All iCamHost™ operating
modes are controlled by the host PC via an I
2
C interface.
Hardware I/O controls include output enable and I
2
C address
offset.
NOTE: iCam
TM
, CamPort™ and iCamHost™ are
trademarks of Silicon Vision, Inc., Fremont, CA.
FEATURES
s
Accommodates different camera configurations based on
a variety of CCD imager resolutions
s
Requires only a small, low-cost 9 pin mini-DIN to connect
to camera
s
Receives the image signal from the camera in digital form
at a frame rate determined by the host
s
Decodes all necessary synchronization and clock signals
from the digital data stream
s
Programmable gamma correction curve in RGB
colourspace
s
Programmable colour-separation matrix
s
Collects image status data within user-defined rectangular
gated zone of CCD sensor
s
Programmable horizontal and vertical aperture correction
s
Pin-strap selectable output format in 16 bit YUV 4:2:2 or 8
bit CCIR 656 YUV 4:2:2
s
Test pattern generator for SMPTE colourbars
s
Bypass mode to output unprocessed 8 bit CCD pixel
samples in the luminance channel
s
Dual iCamPort™ camera input ports, software selectable
s
Completely iVision™ Compatible
768
X 8 X 2
6
SYNC
& CLK
2H LINE
DELAY
FIFO RAM
PORT A
5
5
PORT B
DEMUX
& SYNC
RECOVERY
RAM
CONTROL
C
M
Y
G
COLOUR
MATRIX
CONVERTER
RG B
PIXEL
SEPARATOR
ADDRESS
OFFSET
SERIAL BUS
CONTROLLER
2
I2 C
FIELD &
COLOUR
FLAGS
GAMMA
CORRECTION
COLOUR SPACE
CONVERSION
UV
CHROMINANCE
SUB-SAMPLING
& FILTERING
OUTPUT
FORMATTER
CC IR6 01
16
or
8
OUTPUT
ENABLE
or
CC IR6 56
Y
UV
APERTURE
CORRECTION
CHROMINANCE
& LUMINANCE
METRICS
Y
Fig.1 Functional Block Diagram
VP7610
THEORY OF OPERATION
General Overview
The VP7610 iCamHost™ is a fully synchronous real-time
pipeline pixel processor for converting digitized CCD
photosite samples into co-sited, colour calibrated, gamma
corrected and aperture corrected digital video in an industry-
conventional format similar to analog video decoders. The
VP7610 supports the full iVision™ Command Set for control
of camera head functions such as frame rate, resolution,
exposure and colour depth via the CamPort™ Interface.
2
Access to all registers and functions is provided by an I C state
machine.
Demux and sync recovery
The incoming CCD photosite bytes come in a single nibble at
a time in a “bi-endian” fashion from one of two CamPort™s.
These nibbles are clocked in via a separate pixel clock signal.
The formatting signals such as start of active video, end of
active video, and start of new frame are all encoded into the
nibble stream. The output is an 8 bit byte of CCD sample for
each pixel clock, as well as separate horizontal and vertical
sync signals.
RAM control & 2H line delay FIFO RAM
Since the iCamHost™ assumes an interlaced scanning CCD
with a CMYG colour mosaic format, the colour content is
derived from different locations around where the output video
pixel is desired. Specifically, the first line from the CCD
contains “red-like” colour content, alternating with the
following line containing “blue-like” colour content. The third
line is real-time, and the first opportunity to output properly co-
sited luminance and chrominance as though the colour pixels
were superimposed upon themselves, all on the second line.
Pixel separator
Since the colourspace converter requires the 3 most recent
lines of CCD data, this block handles the shuffling of either the
2 red and 1 blue line, or 2 blue and 1 red line of data.
Colour matrix converter
The input to this converter is derived from the relative sums
and differences of the above 3 lines of sample data, and
processes them through a programmable 3x3 matrix
multiplier. The output is colour-separated and calibrated RGB
samples.
Gamma corrector
Since CRT monitors have a non-linear RGB intensity
response to input signal, gamma correction must be
performed in RGB space as well to prevent cross-coupling
errors between luminance and chrominance. This block is a
programmable 16 line-segment curve generator to provide
not only gamma correction, but any arbitrary contiguous curve
of positive slope, with end points at any level to adjust contrast
and range.
Colourspace converter
Since the output of the processor is to be YUV and not RGB,
a fixed-coefficient 3x3 matrix converter is used.
Chrominance sub-sampling & filtering
Spatial sub-sampling and filtering is performed since the
output sampling format must be reduced from 4:4:4 to 4:2:2
because most video systems do not require more
chrominance data for video camera input.
Output formatter
Devices taking digital video input such as capture, graphics
and compression chips usually require the YUV to be
formatted either in 16 bit (YU then YV) mode or 8 bit (U then
Y then V then Y) mode. The output mode is pin-strap
selectable. An output enable input signal may be used when
sharing a data bus with other video decoders. Other useful
signals such as field and colour flags are also provided.
Aperture corrector
Since both the luminance and chrominance are derived from
spatially spread pixels and the ideal output would be as though
all the pixels were superimposed upon one another, a
programmable vertical and horizontal aperture correction can
be applied to either “soften” or “sharpen” the image.
Scene-sensing luminance and chrominance metrics
There are no hard-wired closed-loop control circuits in the
processor. To achieve great flexibility in control over the
behavior of the camera head and processor system, a user-
defined region of interest is programmed which provides
statistical information about the field of video only within that
region. Peak luminance, total luminance, total red
chrominance and total blue chrominance are provided and
updated after each field.
Serial bus control
To provide read-write control over the registers within the
processor, a standard I
2
C state-machine is provided. Its
address may be offset by 3 bits to preclude address conflicts.
2
VP7610
PERFORMANCE
PARAMETER
CCD Resolution
Field Rate
Video Sample Rate
Video Sample Quantization
Control Signals
Configuration Inputs
Gamma Correction
Output Format
Output Colourspace
Output Signals
Power Consumption
MAXIMUM VALUE OR SPECIFICATION
Up to 768 pixels per line
Up to 60 fields per second
30 MHz. max. input clock rate, 15MHz. max. output clock rate
8 bit samples in 2 nibbles of 4 bits each
Standard I
2
C protocol
I
2
C address offset, output enable
Programmable via 16 arbitrary connected line segments
CCIR601 compliant 4:2:2 digital video, pixels per line=CCD pixels
YCrCb luminance & chrominance
16 bit digital video, H & V sync, 1X & 2X clock, field ID, chroma ID
950mW
STATUS REGISTERS
FUNCTION
Gated Luminance Sum
Gated Luminance Peak
Gate Red Chrominance Sum
Gated Blue Chrominance Sum
SIZE
32 bits
8 bits
32 bits
32 bits
DESCRIPTION
Sum of luminance values within gated zone
Value of peak luminance pixel(s) within gated zone
Sum of red chrominance values within gated zone
Sum of blue chrominance values within gated zone
CONTROL REGISTERS
FUNCTION
Colour Calibration Matrix
Gating Zone Start Pixel
Gating Zone End Pixel
Gamma Correction
Horiz. Aperture Correction
Vert. Aperture Correction
Processor bypass
CamPort
TM
select
Test pattern generator
SIZE
78 bit
16 bits
16 bits
128 bit
4 bits
4 bits
2 bits
1 bit
1 bits
DESCRIPTION
9x9 bit signed coefficients converting CMYG to RGB
8 bits for column # and for row #, in 4 pixel increments
8 bits for column # and for row #, in 4 pixel increments
Locus of 16 points of 8 bits each forms many curves
00H = 0%, 40H = +100%, 70H = +175%, F0H= -175%
00H = 0%, 40H = + 50%, 70H = + 87%, F0H= - 87%
0=normal, 1=pass raw 8 bit samples to Y output pins
0=port A, 1=port B
0=live video, 1=colourbars
3
VP7610
SIGNALS & PINOUT
Pin #
60
54
55
56
59
88
84
85
86
87
91
I/O
In*
In*
In*
In*
In*
In*
In*
In*
In*
In*
Out
Name
CPCLK
CPD3
CPD2
CPD1
CPD0
CPCKB
CPDB3
CPDB2
CPDB1
CPDB0
CPSEL
Description
Clock - This input receives the clock from the CamPort™ camera on port A.
CamPort™ Data Bit 3 - This bus receives the data from the CamPort™ camera on port
A.
CamPort™ Data Bit 2 - Port A
CamPort™ Data Bit 1 - Port A
CamPort™ Data Bit 0 - Port A
CamPort™ B Clock - This input receives the clock from the CamPort™ camera on port
B.
CamPort™ B Data Bit 3 - This bus receives the data from the CamPort™ camera on
port B.
CamPort™ B Data Bit 2
CamPort™ B Data Bit 1
CamPort™ B Data Bit 0
CamPort™ Select Status - When this output is low, the data from CamPort™ A is being
used, when this output is high, the data from CamPort™ B is being used. This pin is
controlled by Bit 3 of the Configuration Register (sub-address = 0x00)
.
Reset Not - When this Schmidtt trigger input is low, the chip is placed into a known
state. When this input is high, the chip can operate.
Luminance Out bit 7 - When CCSEL is low this bus carries the luminance data. When
CCSEL is high this bus carries multiplexed luminance and chrominance data
Luminance Out bit 6
Luminance Out bit 5
Luminance Out bit 4
Luminance Out bit 3
Luminance Out bit 2
Luminance Out bit 1
Luminance Out bit 0
Chrominance Out bit 7 - When CCSEL is low this bus carries the chrominance data.
When CCSEL is high this bus carries a constant value of 0x80 (128).
Chrominance Out bit 6
Chrominance Out bit 5
Chrominance Out bit 4
Chrominance Out bit 3
Chrominance Out bit 2
Chrominance Out bit 1
Chrominance Out bit 0
Clock Out 2X - This clock runs at twice the pixel rate
Clock Out 1X - This clock runs at the pixel rate.
Output Enable - When this input is high, the signals YY[7..0], UV[7..0], HSYNC, VSYNC,
CLK2, CLK1, HACT, VACT, FIELD and BFLAG are driven. When this input is low,
these signals are high-impedance.
44
11
10
9
6
5
4
3
2
23
22
21
20
17
16
15
14
24
27
34
In
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
RSTN
YY7
YY6
YY5
YY4
YY3
YY2
YY1
YY0
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
CLK2
CLK1
OUTEN
* CamPort inputs are TTL levels. All other inputs are CMOS. See Static Electrical Characteristics table.
4
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