Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
VP536E
NTSC/PAL Digital Video Encoder
DS4322 - 3.2 August 1997
FEATURES
s
Converts RGB data (3x8bits) to analog composite
video and S-video
s
Internal video timing generation
s
RGB or YUV input modes
s
Progressive scanning (non-interlaced fields)
display mode optional
s
Separate horizontal and vertical sync outputs
s
68 pin PLCC package
DESCRIPTION
The VP536E converts digital RGB data (3x8bits) into
analog NTSC/PAL composite video and S-video signals. The
outputs are capable of driving doubly terminated 75 ohm
loads with standard video levels.
The device will also accept YUV data. Progressive scan
(non-interlaced fields) video display is available in both
NTSC and PAL modes.
The output pixel rate is approximately 7 times Fsc (color
subcarrier frequency) for NTSC (6.6 times Fsc for PAL)
which is approximately 25MHz. Input pixel rate is half this
frequency; approximately 12.5MHz.
All the necessary synchronization signals are generated
internally. Digital horizontal and vertical sync outputs are
available for use by the host system.
The rise and fall times of sync, burst envelope and video
blanking are internally controlled to be within composite
video specifications.
Two 8-bit digital to analog converters (DACs) are used
to convert the digital luminance and chrominance data into
analog signals. An inverted composite video signal is
generated by summing the complimentary current outputs of
each DAC. An internally generated reference voltage
provides the biasing for the DACs.
APPLICATIONS
s
s
s
s
s
s
Multi-media
Video Games
PC’s
Graphics
Display Adaptors
Video Effects Processors
CTRLB1
VS
CTRLB2
COMPOSITE SYNC
VIDEO TIMING GENERATOR
HS
MATRIX
BYPASS
BURST
GATE
R0:7
Y
RGB
INTER-
POLATOR
(SIN X/X)
-1
PRECOMPEN-
SATION
LUMAOUT
LUMA
DAC
COMP-
OUTB
G0:7
TO
YUV
MATRIX
U
CHROMA
LOW-PASS
FILTER
INTER-
POLATOR
BANDPASS
MODULATOR
FILTER
CHROMA
DAC
CHROMAOUT
B0:7
V
COLOR SUBCARRIER
GENERATOR
CLK25I CLK12I
CLK25O CLK12O
CTRLA1
CTRLA2
CTRLA3
Fig. 1. Functional Block Diagram
VP536E
NTSC/PAL Video Standards
Both NTSC (4-field, 525 lines) and PAL (8-field, 625
lines) video standards are supported by the VP536E. All
raster synchronization, color subcarrier and burst
characteristics are adapted to the standard selected.
However, different input clock frequencies are necessary for
each of the two video standards. For the NTSC mode of
operation, input clock frequencies of 25.048948MHz. and
12.524474MHz. are required. For the PAL mode of
operation, the required input clock frequencies are
29.500000MHz. and 14.750000MHz. The two input clock
frequencies in each of the video standards are related by a
ratio of 2.
The mode of operation is selected through the CTRLB1
and CTRLB2 pins as shown in Table 1.
(VS) pulse signals. The HS and VS signals are negative true
pulses coincident with the sync pulses in the output video
signals.
The HS signal has the same duration as a standard
horizontal sync pulse but is continuous through the vertical
sync interval.
Input Pixel Data Format
Input pixel data may be in one of two formats; pre-
gamma corrected RGB and YUV. This format is controlled by
the state of theCTRLA1, CTRLA2 and CTRLA3 pins as
shown in Table 2.
The RGB input data coding is straight binary and is in
the range of 0-255. In the YUV input mode, Y, U and V data is
presented on the R, B and G input data buses, respectively.
Y data coding is binary and is in the range of 0-247. U and V
coding is in two’s compliment binary. U is in the range of -
102 to +102 and V is in the range of -107 to +107.
Progressive Scan Display
Progressive scan (non-interlaced fields) display mode is
available for semi-NTSC and semi-PAL video applications.
For NTSC, there are 263 lines in each field instead of
262.5 lines per field in a normal NTSC display. Thus, 263
lines of field 2 data are scanned as field 1 resulting in 526
lines per ‘frame’.
For PAL, there are 313 lines in each field instead of
312.5 lines per field in a normal PAL display. Thus, 313 lines
of field 2 data are scanned as field 1, resulting in 626 lines
per ‘frame’.
Progressive scanning display mode is selected through
the CTRLB1 and CTRLB2 pins as shown in Table 1.
Table 1: VP536E Modes of Operation
CTRLB2
0
0
1
1
CTRLB1
0
1
0
1
Video Standard
Dithering
In applications where the input RGB/YUV data has
been subject to video compression, visual artefacts may
occur in the video display depending on the type and quality
of video compression employed.
The VP536E incorporates dithering techniques on the
incoming RGB data and on the internal luminance data in
order to minimize any artefacts.
Each of these dithering techniques can be enabled or
disabled through the CTRLA1 and CTRLA2 pins as shown in
Table 2 below.
Table 2: Input Pixel Data Format and Dithering Selection
CTRLA3 CTRLA2 CTRLA1
Input Pixel Data Format
RGB input dither ON, Luma
dither OFF
RGB input dither ON, Luma
dither ON
RGB input dither OFF, Luma
dither ON
RGB input dither OFF, Luma
dither OFF
YUV input, Luma dither ON
YUV input, Luma dither OFF
reserved
reserved
NTSC
Progressive Scan NTSC
PAL
Progressive Scan PAL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NOTE: CTRLB1 & CTRLB2 are internally pulled low, therefore, if left
unconnected, NTSC is the default mode of operation.
Video Timing
The VP536E has an internal sync generator which
produces video timing signals appropriate to the mode of
operation. All timing signals are derived from the two input
clocks. These clocks are input on the CLK25I pin
(25.048948MHz:NTSC/29.5MHz:PAL) and the CLK12I pin
(12.52444MHz:NTSC/14.75MHz:PAL). The two input clock
frequencies for NTSC and PAL are related by a ratio of 2.
The lower frequency corresponds to the input pixel data
rate. Input pixel data is latched in on the rising edge of the
CLK12I clock.
The clocks must be derived from a crystal controlled
oscillator in order to avoid timing, chroma frequency and
modulation errors.
The video timing generator produces the internal
composite sync, blanking and burst gate as well as
externally available horizontal sync (HS) and vertical sync
NOTE: CTRLA1 is internally pulled high, while CTRLA2 & CTRLA3
are internally pulled low; therefore if left unconnected, pre-gamma
corrected RGB is the default input pixel data format with input RGB
and luma dithering enabled.
Video Blanking
The VP536E automatically performs standard
composite video blanking. Lines 1-17, 261-279, 523-525
inclusive, as well as the last half of line 260 and the first half
of line 280 are blanked in the NTSC mode. In PAL mode,
lines 1-22, 311-335, 624-625 inclusive, as well as the last
half of line 623 and the first half of line 23 are blanked.
2
VP536E
The host pixel data can be phased relative to the active
video timing by counting the CLK12I clock periods from the
rising edge of HS. NTSC active video starts 48 CLK12I clock
cycles after the rising edge of the horizontal sync pulse
output, and PAL active video starts 58 CLK12I clock periods
after the rising edge of HS (HS and VS pulse edges coincide
with the rising edge of the CLK12I clock).
Input pixel data is ignored during the composite
blanking periods.
external gain setting resistors between the LUMAGAIN,
CHROMAGAIN pins and GND.
For the correct DAC gains in the NTSC & PAL modes,
the LUMAGAIN resistance should be 837ohms. The
CHROMAGAIN resistance should be 520ohms for the
proper corresponding chroma amplitude (including sinx/x
compensation).
Color Space Matrix
The RGB color space is converted to a YUV color
space, using a transformation matrix defined by the NTSC
and PAL colorimetry definitions. If the input data format is
YUV, this block is bypassed without affecting the overall data
latency.
Luminance, Chrominance & Composite Video
Outputs
The Luminance video output (LUMAOUT pin) drives a
37.5 ohm load at 1.0V, sync tip to peak white. It contains only
the image’s luminance content plus the composite
synchronization pulses.
The chrominance video output (CHROMAOUT pin)
drives a 37.5 ohm load at levels proportional in amplitude to
the luma output. This output has a fixed offset current which
will produce approximately a 0.5V DC bias across the 37.5
ohm load. Burst is injected with appropriate timing relative to
the luma signal.
Luma, Chroma and true Composite video signals may
be obtained simultaneously through the use of an external
inverting video amplifier with the inverted composite video
output (COMPOUTB pin).
The inverted composite video output has a fixed DC
offset. Sync tip is the most positive voltage and is
approximately 1.5V with a 37.5 ohm load.
The NTSC and PAL output video waveforms of the
luma, chroma and inverted composite signals for 100%
amplitude, 100% saturated color bars are shown in Figs. 3-8.
Interpolator
The luminance and chrominance data is separately
passed through interpolating filters to produce output
sampling rates double that of the incoming pixel rate. This
reduces the sinx/x distortion that is inherent in the digital to
analog converters and also simplifies the analog
reconstruction filter requirements.
Sinx/x Distortion Precompensation
The luminance data is precompensated for the sinx/x
distortion that is inherent in the digital to analog converters.
Since the chrominance data is contained within a relatively
narrow frequency range, it’s sinx/x distortion is compensated
for by increasing the gain of the chrominance DAC by a fixed
amount.
Digital To Analog Converters
The VP536E contains two 8-bit digital to analog
converters which produce the analog video signals. The
DACs use a current steering architecture in which bit
currents are routed to one of two outputs; thus each DAC
has a true and complimentary output. The use of identical
current sources and current steering their outputs means
that monotonicity is guaranteed. An on-chip voltage
reference of 1.0V (typ.) provides the necessary biasing.
However, the VP536E may be used in applications where an
external 1V reference is provided, in which case the external
reference should be temperature compensated and provide
a low impedance output.
The full-scale output currents of the DACs is set by
external resistors between the LUMAGAIN, CHROMAGAIN
and GND pins. An on-chip loop amplifier stabilizes the full-
scale output current against temperature and power supply
variations.
By summing the complimentary current outputs of the
two DACs, an inverted composite video signal is obtained.
Note that this signal has a DC offset. The analog outputs of
the VP536E are capable of directly driving a 37.5 ohm load,
such as a doubly terminated 75 ohm co-axial cable.
Extendable S-Video Bandwidth
The bandwidth of color baseband signals is typically
limited in order to avoid modulation problems that develop in
composite video due to the interleaving of the chrominance
and luminance frequency components. The VP536E can use
either traditional bandwidth limited or extended bandwidth
baseband signals. For applications where the composite
signal is the main source of the video display, it is
recommended that bandwidth limiting be used in order to
reduce “dot-crawl” effects in the display. For S-Video
applications where the luma and chroma signals are
separate, enabling the extended bandwidth will result in
improved picture definition.
The enabling/disabling of this bandwidth extension is
controlled through the TCSPK pin as shown below.
Table 3: Bandwidth Control
TCSPK
0
1
Chroma Bandwidth
Extended Bandwidth
Limited Bandwidth
DAC Gain Adjust
The gains of the luma and chroma DACs are
independently adjustable. The gains are adjusted using the
NOTE: TCSPK is internally pulled LOW, therefore
Extended Bandwidth is the default selection.
3
VP536E
Master Reset
The VP536E can be initialized with the RESET pin. This
is an active low signal and must be active for a minimum of 2
CLK12I clock periods in order for the VP536E to be reset.
Video Timing Reset
The VP536E also features the ability to independently
reset the video timing generator without affecting the data
path. The TSURST pin controls this function. Taking this pin
high resets the video timing generator. If this pin is left open,
it is internally pulled low.
48 Periods
CLK12I
HS
Line 1
Line 2
Line 3
Line 4
Line 17
VS
Field 1
Line 17
RGB/YUV
INPUT DATA
Fig. 2a. NTSC Input Timing Diagram
1st
pixel
2nd
pixel
58Periods
CLK12I
HS
Line 1
Line 2
Line 3
Line 4
Line 23
VS
Field 1
Line 23
RGB/YUV
INPUT DATA
Fig. 2b. PAL Input Timing Diagram
1st
pixel
2nd
pixel
NOTE:
1. Coincident falling edges of HS and VS denote the start of an odd field.
2. VS is low during the first 3 lines in each NTSC field and during the first 2
1
/
2
lines in each PAL field.
3. Input pixel data is ignored during composite blanking periods.
4
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
