CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379.1 for
details.)
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER
ISET Current Source
Current Limit Amp Offset Voltage
V
DD
= 12V, T
A
= T
J
= 0
o
C to 85
o
C, Unless Otherwise Specified
SYMBOL
I
ISET
V
ISET
- V
ISEN
C
TIM
_Vth
pd_woc_amp
pd_oc_amp
I
GATE
OC_GATE_I_4V
WOC_GATE_I_4V
12V
UV_VTH
12V
UV_VTH_dis
12VG
5V
UV_VTH
5V
UV_VTH_dis
5VG
I
VDD
V
DD_POR_L2H
V
DD_POR_H2L
V
DD_POR_HYS
PWRN_V
PWR_Vth
PWR_hys
PWRN_I
C
TIM
_ichg0
V
CTIM
= 0V
VDD Low to High
VDD High to Low
V
DD_POR_L2H -
V
DD_POR_H2L
PWRON Pin Open
GATE Voltage
GATE Voltage
CTIM Voltage
V
GATE
to 10.8V
V
GATE
to 10.8V
V
GATE
to = 6V
Overcurrent
Severe Overcurrent
8.4
45
0.5
9.2
TEST CONDITIONS
MIN
18.5
-6
1.3
-
TYP
20
0
1.8
100
600
10
75
0.8
9.6
1.5
10
11.6
MAX UNITS
21.5
6
2.3
-
µA
mV
V
ns
ns
µA
mA
A
V
V
-
4.5
V
V
V
-
5
9
8.7
0.6
-
2.0
250
25
23
23
88
170
V
mA
V
V
V
V
V
mV
µA
µA
mA
µA
µA
Current Limit Time-Out Threshold Voltage
GATE Response Time To Severe
Overcurrent
GATE Response Time to Overcurrent
GATE Turn-On Current
GATE Pull down Current
GATE Pull down Current
HIP1015 Undervoltage Threshold
HIP1015 Undervoltage Disabled
HIP1015 GATE High Voltage
HIP1016 Undervoltage Threshold
HIP1016 Undervoltage Disabled
HIP1016 GATE High Voltage
V
DD
Supply Current
V
DD
POR Rising Threshold
V
DD
POR Falling Threshold
V
DD
POR Threshold Hysteresis
PWRON Pull-up Voltage
PWRON Rising Threshold
PWRON Hysteresis
PWRON Pull-Up Current
C
TIM
Charging Current
C
TIM
Fault pull-up Current
HIP1015 ISEN Current
HIP1016 ISEN Current
V
DD
+1.9V V
DD
+2.5V
V
DD
+4.5V
4.0
V
DD
-3V
V
DD
-1.5V
-
7.8
7.5
0.1
2.7
1.4
130
9
16
16
V
DD
+5V
4.35
V
DD
-2.5V
V
DD
3
8.4
8.1
0.3
3.2
1.7
170
17
20
20
72
145
ISEN_5V_I
ISEN_5V_I
41
100
3
HIP1015,HIP1016
HIP1015, HIP1016 Description and Operation
The HIP1015 and HIP1016 are single power supply
distribution controllers for generic hot swap applications. The
HIP1015 is targeted for +12V switching applications
whereas the HIP1016 is targeted for +5V applications as
each has an undervoltage (UV) threshold level ~17% lower
than the nominal +12V and +5V, respectively.
The HIP1015 and HIP1016 features include a highly
accurate programmable Overcurrent (OC) detecting
comparator, programmable current limiting regulation with
programmable time delay to latch off and programmable soft
start turn-on ramp all set with a minimum of external passive
components. The HIP1015 and HIP1016 also include severe
overcurrent protection that immediately shuts down the
MOSFET switch should the load current cause the OC
voltage threshold to exceed the programmed OC level by
150mV. Additionally the HIP1015 and HIP1016 have an UV
indicator and an OC latch indicator.
Upon initial power up, the HIP1015 or HIP1016 can either
isolate the voltage supply from the load by holding the external
N-Channel MOSFET switch off or apply the supply rail voltage
directly to the load for true hot swap capability. In either case
the HIP1015 and HIP1016 turns on in a soft start mode
protecting the supply rail from sudden in-rush current. The
PWRON pin must be pulled low for the device to isolate the
power supply from the load by holding the external N-channel
MOSFET off, otherwise with the PWRON pin held high or
floating the HIP1015 and HIP1016 will be in true hot swap
mode.
At turn-on, the gate capacitor of the external N-Channel
MOSFET is charged with a 10µA current source resulting in
a programmable ramp (soft start turn-on). The internal
HIP1015 charge pump supplies the gate drive for the 12V
supply switch driving that gate to V
DD
+5V. The HIP1016
gate drive is limited to the chip bias voltage.
Load current passes through the external current sense
resistor. When the voltage across the sense resistor
exceeds the user programmed Overcurrent voltage
threshold value, (See Table 1 for R
ISET
programming
resistor value and resulting nominal overcurrent threshold
voltage, V
OC
) the controller enters current regulation. At this
time, the time-out capacitor, on C
TIM
pin starts charging with
a 20mA current source and the controller enters the current
limit time to latch-off period. The length of the current limit
time to latch-off period is set by the single external capacitor
(See Table 2 for CTIM capacitor value and resulting nominal
current limited time out to latch-off period.) placed from the
CTIM pin (pin 6) to ground. The programmed current level is
held until either the OC event passes or the time out period
expires. If the former is the case then the N-Channel
MOSFET is fully enhanced and the C
TIM
capacitor is
discharged. Once CTIM charges to 1.87V, signaling that the
time out period has expired an internal latch is set whereby
the FET gate is quickly pulled to 0V turning off the N-
Channel MOSFET switch, isolating the faulty load.
TABLE 1.
R
ISET
RESISTOR
10kΩ
4.99kΩ
2.5kΩ
750Ω
NOTE: Nominal Vth = R
ISET
x 20µA.
TABLE 2.
C
TIM
CAPACITOR
0.022µF
0.047µF
0.1µF
NOMINAL CURRENT LIMITED PERIOD
2ms
4.4ms
9.3ms
NOMINAL OC VTH
200mV
100mV
50mV
15mV
NOTE: Nominal time-out period in seconds = C
TIM
x 93kΩ.
The HIP1015 and HIP1016 respond to a severe overcurrent
load (defined as a voltage across the sense resistor >150mV
over the OC Vth set point) by immediately, driving the N-
Channel MOSFET gate to 0V in less than 1µs. The gate
voltage is then slowly ramped up turning on the N-Channel
MOSFET to the programmed current limit level, this is the
start of the time out period.
Upon an UV condition the PGOOD signal will pull low when
tied high through a resistor to the logic supply. This pin is an
UV fault indicator. For an OC latch off indication, monitor
CTIM, pin 6. This pin will rise rapidly from 1.9V to 12V once
the time out period expires.
The HIP1015 and HIP1016 are reset after an OC latch-off
condition by a low level on the PWRON pin and is turned on
by the PWRON pin being driven high.
Application Considerations
During the
Time-Out Delay Period
with the HIP1015 and
HIP1016 in current limit mode, the V
GS
of the external N-
Channel MOSFETs is reduced driving the N-Channel
MOSFET switch into a high r
DS(ON)
state. Thus avoid
extended time out periods as the external N-Channel
MOSFETs may be damaged or destroyed due to excessive
internal power dissipation. Refer to the MOSFET
manufacturers data sheet for SOA information.
With the high levels of inrush current e.g., highly capacitive
loads and motor start up currents,
choosing the current
limiting level
is crucial to provide both protection and still
allow for this inrush current without latching off. Consider this
in addition to the time out delay when choosing MOSFETs
for your design.
4
HIP1015,HIP1016
Physical layout of R
SENSE
resistor
is critical to avoid the
possibility of false overcurrent occurrences. Ideally trace
routing between the R
SENSE
resistors and the HIP1015 and
HIP1016 is direct and as short as possible with zero current
in the sense lines. (See Figure 1.)
Biasing the HIP1016
Table 3 gives typical component values for biasing the
HIP1016 in a 48V application. The formulas and calculations
deriving these values are also shown below.
TABLE 3. TYPICAL VALUES FOR A -48V HOT SWAP
APPLICATION
CORRECT
INCORRECT
SYMBOL
R
CL
DD1
1.58kΩ, 1W
PARAMETER
12V Zener Diode, 50mA Reverse Current
TO ISEN AND
R
ISET
CURRENT
SENSE RESISTOR
When using the HIP1016 to control -48V, a Zener diode may
be used to provide the +12V bias to the chip. If a Zener is
used then a current limit resistor should also be used.
Several items must be taken into account when choosing
values for the current limit resistor (R
CL
) and Zener Diode
(DD1):
• The variation of the V
BUS
(in this case, -48V)
FIGURE 1. SENSE RESISTOR PCB LAYOUT
• The chip supply current needs for all functional conditions
• The power rating of R
CL
.
• The current rating of DD1
Using the HIP1016 as a -48V Low Side Hot
Swap Power Controller
To supply the required V
DD
, it is necessary to maintain the
chip supply 12V above the -48V bus. This may be
accomplished with a +12V Regulator between the voltage
rail and pin 5 (VDD). By using a Regulator, the designer may
ignore the bus voltage variations. However, a low-cost
alternative is to use a Zener diode (See Figure 2 for typical
5A load control ) this option is detailed below.
Note that in this configuration the PGOOD feature (pin 7) is
not operational.
HUF7554S3S
LOAD
Formulas
1. Sizing R
CL
:
R
CL
= (V
BUS,MIN
- 12)/I
CHIP
2. Power Rating of R
CL
:
P
RCL
= I
C
(V
BUS,MAX
- 12)
3. DD1 Current Rating:
I
DD1
= (V
BUS,MAX
- 12)/R
CL
Example:
A typical -48V supply may vary from -36 to -72V. Therefore,
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