White Electronic Designs
WV3HG2128M64EEU-D6
ADVANCED*
2GB – 2x128Mx64 DDR2 SDRAM UNBUFFERED
FEATURES
Unbuffered 240-pin, dual in-line memory module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
V
CC
= V
CCQ
= 1.8V
V
CCSPD
= +1.7V to +3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms 8,192 cycle refresh)
Gold edge contacts
Product is lead-free
Dual Rank
RoHS compliant
Package option
• 240 Pin DIMM
• 30.00mm (1.181") TYP
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity function
DESCRIPTION
The WV3HG2128M64EEU is a 2x128Mx64 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of sixteen 128Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
OPERATING FREQUENCIES
PC2-6400*
Clock Speed
CL-t
RCD
-t
RP
* Consult factory for availability
PC2-5300*
333MHz
5-5-5
PC2-4300
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
400MHz
6-6-6
October 2006
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
V
CC
CKE0
V
CC
BA2
NC
V
CC
A11
A7
V
CC
A5
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
A4
V
CC
A2
V
CC
V
SS
V
SS
V
CC
NC
V
CC
A10/AP
BA0
V
CC
WE#
CAS#
V
CC
CS1#
ODT1
V
CCQ
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
CK1
CK1#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
V
CC
CKE1
V
CC
NC
NC
V
CC
A12
A9
V
CC
A8
A6
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
V
CC
A3
A1
V
CC
CK0
CK0#
V
CC
A0
V
CC
BA1
V
CC
RAS#
CS0#
V
CC
ODT0
A13
V
CC
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK2
CK2#
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
CC
SPD
SA0
SA1
2
WV3HG2128M64EEU-D6
ADVANCED
PIN NAMES
Pin Name
A0-A13
BA0,BA2
DQ0-DQ63
DQS0-DQS7
DQS0#-DQS7#
DM0-DM7
ODT0, ODT1
CK0,CK0#-CK2,CK2#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
SA0-SA2
SDA
SCL
V
CC
V
SS
V
REF
V
CC
SPD
NC
Function
Address Inputs
SDRAM Bank Address
Data Input/Output
Data strobes
Data strobes complement
Data masks
On-die termination control
Clock Inputs
Clock Enables
Chip Selects
Row Address Strobe
Column Address Strobe
Write Enable
SPD address
SPD Data Input/Output
SPD Clock Input
Core Power (1.8V)
Ground
Power Supply for Reference
SPD Power
Spare pins, No connect
October 2006
Rev. 2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WV3HG2128M64EEU-D6
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQS0#
DM0
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DQS4
DQS4#
DM4
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1#
DM1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS5
DQS5#
DM5
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS6
DQS6#
DM6
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3#
DM3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQS7
DQS7#
DM7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DM/
RDQS
CS#
DQS
DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ30
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
V
CCSPD
V
CC\
V
CCQ
VREF
V
SS
Serical PD
SCL
WP
Serial PD
SDA
A0
SA0
A1
SA1
A2
SA2
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
*Clock Wiring
Clock
Input
*CK0/CK0#
*CK1/CK1#
*CK2/CK2#
CS0#
CS1#
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
CS0#: DDR 2 SDRAMs
CS1#: DDR 2 SDRAMs
BA0-BA2: DDR 2 SDRAMs
A0-A13: DDR 2 SDRAMs
RAS#: DDR 2 SDRAMs
CAS#: DDR 2 SDRAMs
WE#: DDR 2 SDRAMs
CKE0: DDR 2 SDRAMs
CKE1: DDR 2 SDRAMs
ODT0: DDR 2 SDRAMs
ODT1: DDR 2 SDRAMs
DDR2 SDRAMs
4 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ, DM, DQS/DQS# resistors: 5.1 Ohms +/-5%
2. BAx, Ax RAS#, CAS#, WE# resistors: 5.1 Ohms +/- 5%
October 2006
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
All voltages referenced to V
SS
Parameter
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Symbol
V
CC
V
REF
V
TT
V
CCSPD
Min
1.7
0.49 x V
CC
V
REF
-0.04
1.7
Typical
1.8
0.50 x V
CC
V
REF
-
WV3HG2128M64EEU-D6
ADVANCED
DC OPERATING CONDITIONS
Max
1.9
0.51 x V
CC
V
REF
+0.04
3.6
Unit
V
V
V
V
Notes
3
1
2
Notes:
1
V
REF
is expected to equal V
CC/2
of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
V
REF
may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on V
REF
may not exceed +/-2 percent of V
REF
. This measurement is to be taken at the nearest V
REF
bypass capacitor.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
3. V
CCQ
of all IC's are tied to V
CC
.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
IN
, V
OUT
T
STG
Parameter
Voltage on V
CC
pin relative to V
SS
Voltage on any pin relative to V
SS
Storage Temperature
Command/Address,
RAS#, CAS#, WE#,
I
L
Input leakage current; Any input 0V<V
IN
<V
CC
; V
REF
input
0V,V
IN
,0.95V; Other pins not under test = 0V
CS#, CKE
CK, CK#
DM
I
OZ
I
VREF
Output leakage current; 0V<V
IN
<V
CC
; DQs and ODT are disable
V
REF
leakage current; V
REF
= Valid V
REF
level
DQ, DQS, DQS#
Min
-0.5
-0.5
-55
-80
-40
-30
-10
-10
-32
Max
2.3
2.3
100
80
40
30
10
10
32
Units
V
V
°C
μA
μA
μA
μA
μA
μA
INPUT/OUTPUT CAPACITANCE
T
A
= 25°C, f = 100MHz, V
CC
= 1.8V
Parameter
Input Capacitance (A0-A13, BA0~BA2, RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1), (ODT0, ODT1)
Input Capacitance (CS0#, CS1#))
Input Capacitance (CK0, CK0#-CK2, CK2#)
Input Capacitance (DQS0~DQS7), (DM0-DM7)
Input Capacitance (DQ0~DQ63)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5 (665)
C
IN5 (534, 403)
C
OUT (665)
C
OUT (534, 403)
Min
20
12
12
10
9
9
9
9
Max
36
20
20
16
11
12
11
12
Unit
pF
pF
pF
pF
pF
pF
pF
pF
October 2006
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
Parameter
Operating Temperature (Commercial)
Symbol
TOPER
WV3HG2128M64EEU-D6
ADVANCED
OPERATING TEMPERATURE CONDITION
Rating
0ºC to 85ºC
Units
ºC
Notes
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2.
2. At 0 - 85
ºC, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Symbol
V
IH(DC)
V
IL(DC)
Min
V
REF
+ 0.125
-0.300
Max
V
CC
+ 0.300
V
REF
- 0.125
Units
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
AC Input Low (Logic 1) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage DDR2-667
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0) Voltage DDR2-667
Symbol
V
IL(AC)
V
IH(AC)
V
IL(AC)
V
IL(AC)
Min
V
REF
+ 0.250
V
REF
+ 0.200
V
REF
- 0.250
V
REF
- 0.200
Max
Units
V
V
V
V
October 2006
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
