SMN18T50FD
Advanced N-Ch Power MOSFET
SWITCHING REGULATOR APPLICATION
Features
Drain-Source breakdown voltage: BV
DSS
= 500V
Low gate charge: Q
g
=65nC (Typ.)
Low drain-source On resistance: R
DS(on)
=0.21Ω (Typ.)
100% avalanche tested
RoHS compliant device
Ordering Information
Part Number
SMN18T50FD
Marking
SMN18T50
Package
TO-220F-3L
GDS
TO-220F-3L
Marking Information
Column 1: Manufacturer
Column 2: Production Information
e.g.) FYMDD
-. F: Factory Management Code
-. YMDD: Date Code (Year, Month, Date)
Column 3: Device Code
AUK
AUK
FYMDD
Δ
YMDD
SMN18T50
SDB20D45
Absolute maximum ratings
(T
C
=25C unless otherwise noted)
Characteristic
Drain-source voltage
Gate-source voltage
Drain current (DC)
*
Drain current (Pulsed)
*
Single pulsed avalanche energy
(Note 2)
Repetitive avalanche current
(Note 1)
Repetitive avalanche energy
(Note 1)
Power dissipation
Peak diode recovery dv/dt
(Note 3)
Junction temperature
Storage temperature range
* Drain current limited by maximum junction temperature
Symbol
V
DSS
V
GSS
I
D
T
c
=25C
T
c
=100C
I
DM
E
AS
I
AR
E
AR
P
D
dv/dt
T
J
T
stg
Rating
500
30
18
11.4
72
900
18
4.8
48
4.5
150
-55~150
Unit
V
V
A
A
A
mJ
A
mJ
W
V/ns
C
C
Rev. date: 27-MAR-13
KSD-T0O097-001
www.auk.co.kr
1 of 8
SMN18T50FD
Thermal Characteristics
Characteristic
Thermal resistance, junction to case
Thermal resistance, junction to ambient
Symbol
R
th(j-c)
R
th(j-a)
Rating
Max. 2.6
Max. 62.5
Unit
C/W
Electrical Characteristics
(T
C
=25C unless otherwise noted)
Characteristic
Drain-source breakdown voltage
Gate threshold voltage
Drain-source cut-off current
Gate leakage current
Drain-source on-resistance
Forward transfer conductance
(Note 4)
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
(Note 4,5)
Rise time
(Note 4,5)
Turn-off delay time
(Note 4,5)
Fall time
(Note 4,5)
Total gate charge
(Note 4,5)
Gate-source charge
(Note 4,5)
Gate-drain charge
(Note 4,5)
Symbol
BV
DSS
V
GS(th)
I
DSS
I
GSS
R
DS(ON)
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
V
DS
=400V, V
GS
=10V,
I
D
=18A
V
DD
=250V, I
D
=18A,
R
G
=25Ω
V
DS
=25V, V
GS
=0V,
f=1.0MHz
Test Condition
I
D
=250uA, V
GS
=0
I
D
=250uA, V
DS
=V
GS
V
DS
=500V, V
GS
=0V
V
DS
=400V, T
c
=125
C
V
DS
=0V, V
GS
=30V
V
GS
=10V, I
D
=9A
V
DS
=10V, I
D
=9A
Min.
500
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ.
-
-
-
-
-
0.21
24.6
3120
355
27
95
375
100
105
65
17.6
18.4
Max.
-
4
1
100
100
0.26
-
-
-
-
-
-
-
-
85
-
-
nC
ns
pF
Unit
V
V
uA
uA
nA
S
Source-Drain Diode Ratings and Characteristics
(T
C
=25C unless otherwise noted)
Characteristic
Source current (DC)
Source current (Pulsed)
Forward voltage
Reverse recovery time
(Note 4,5)
Reverse recovery charge
(Note 4,5)
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
Test Condition
Integral reverse diode
in the MOSFET
V
GS
=0V, I
S
=18A
I
S
=18A, V
GS
=0V
dI
S
/dt=100A/us
Min.
-
-
-
-
-
Typ.
-
-
-
507
7.2
Max.
18
72
1.4
-
-
Unit
A
A
V
ns
uC
Note:
1. Repeated rating: Pulse width limited by safe operating area
2. L=5mH, I
AS
=18A, V
DD
=50V, R
G
=25, Starting T
J
=25C
3. I
S
≤18A,
di/dt≤200A/us, V
DD
≤BV
DSS
, Starting T
J
=25C
4. Pulse test: Pulse width≤300us, Duty cycle≤2%
5. Essentially independent of operating temperature typical characteristics
Rev. date: 27-MAR-13
KSD-T0O097-001
www.auk.co.kr
2 of 8
SMN18T50FD
Electrical Characteristics Curve
Fig. 1 I
D
- V
DS
℃
Fig. 2 I
D
– V
GS
-
Fig. 3 R
DS(ON)
- I
D
℃
Fig. 4 I
DR
- V
SD
60
Reverse Drain Current, I
DR
[A]
V
GS =
0V
250
㎲
Pulse Test
50
150
℃
40
30
25
℃
20
10
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Source - Drain Voltage, V
SD
[V]
Fig. 5 Capacitance - V
DS
Fig. 6 V
GS
- Q
G
Note
I
D
=18A
Tc=25
10
V
DD
=400V
Gate-source voltage V
GS
[V]
5
0
0
15
30
45
60
75
Total Gate Charge Qg [nC]
Rev. date: 27-MAR-13
KSD-T0O097-001
www.auk.co.kr
3 of 8
SMN18T50FD
Electrical Characteristics Curve
(Continue)
Fig. 7 BV
DSS
- T
J
Fig. 8 R
DS(ON)
- T
J
3.0
Note
1.V
GS
=10A
2. I
D
=9A
2.5
R
DS(on) '
(Nomalized)
2.0
1.5
1.0
0.5
0.0
-50
-25
0
25
50
75
100
125
150
175
C
Junction Temperature, T
J
[°C]
Fig. 9 I
D
- T
C
Fig. 10 Safe Operating Area
Fig. 11 Transient Thermal Impedance
Rev. date: 27-MAR-13
KSD-T0O097-001
www.auk.co.kr
4 of 8
SMN18T50FD
Fig. 12 Gate Charge Test Circuit & Waveform
Fig. 13 Resistive Switching Test Circuit & Waveform
Fig. 14 E
AS
Test Circuit & Waveform
Rev. date: 27-MAR-13
KSD-T0O097-001
www.auk.co.kr
5 of 8
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