82541 Family of Gigabit Ethernet
Controllers
Networking Silicon - 82541(PI/GI/EI)
Datasheet
Product Features
■
■
■
PCI Bus
— PCI revision 2.3, 32-bit, 33/66 MHz
— Algorithms that optimally use advanced PCI,
MWI, MRM, and MRL commands
— CLK_RUN# signal
— 3.3 V (5 V tolerant PCI signaling)
MAC Specific
— Low-latency transmit and receive queues
— IEEE 802.3x-compliant flow-control support
with software-controllable thresholds
— Caches up to 64 packet descriptors in a single
burst
— Programmable host memory receive buffers
(256 B to 16 KB) and cache line size (16 B to
256 B)
— Wide, optimized internal data path
architecture
— 64 KB configurable Transmit and Receive
FIFO buffers
PHY Specific
— Integrated for 10/100/1000 Mb/s full- and
half-duplex operation
— IEEE 802.3ab Auto-Negotiation and PHY
compliance and compatibility
— State-of-the-art DSP architecture implements
digital adaptive equalization, echo and cross-
talk cancellation
— Automatic polarity detection
— Automatic detection of cable lengths and
MDI vs. MDI-X cable at all speeds
■
■
■
■
Host Off-Loading
— Transmit and receive IP, TCP, and UDP
checksum off-loading capabilities
— Transmit TCP segmentation and advanced
packed filtering
— IEEE 802.1Q VLAN tag insertion and
stripping and packet filtering for up to 4096
VLAN tags
— Jumbo frame support up to 16 KB
— Intelligent Interrupt generation (multiple
packets per interrupt)
Manageability
— On-chip SMBus 2.0 port
— ASF 1.0 and 2.0
— Compliance with PCI Power Management
v1.1/ACPI v2.0
— Wake on LAN* (WoL) support
— Smart Power Down mode when no signal is
detected on the wire
— Power Save mode switches link speed from
1000 Mb/s down to 10 or 100 Mb/s when on
battery power
Additional Device
— Four programmable LED outputs
— On-chip power regulator control circuitry
— BIOS LAN Disable pin
— JTAG (IEEE 1149.1) Test Access Port built
in silicon (3.3 V, 5 V tolerant PCI signaling)
Lead-free
a
196-pin Ball Grid Array (BGA).
Devices that are lead-free are marked with a
circled “e1” and have the product code:
LUxxxxxx.
a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at
<1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other
Restriction on Hazardous Substances (RoHS)-banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as previous versions of
the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales represen-
tative
318138-002
Revision 2.7
Revision History
Revision
Date
Aug 2002
Sep 2002
Revision
0.25
0.75
• Initial Release.
Description
• Changed package diagram to molded plastic BGA.
• Added DC/AC specifications.
• Corrected pinout information.
• Identified FIFO as 64 KB and verified ballout tables.
• Added 82547GI coverage.
• Signals CLKR_CAP and XTAL_CAP changed to RSVD_NC and NC, respectively.
• Added Architecture Overview chapter.
• Update signal names to match Design Guide and EEPROM Map and Program-
ming Application Note.
• Updated lead-free information.
• Added information about migrating from a 2-layer 0.36 mm wide-trace substrate
to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and
Pinout Information.
• Added statement that no changes to existing soldering processes are needed for
the 2-layer 0.32 mm wide-trace substrate change in the section describing “Pack-
age Information”.
• Added new maximum values for DC supply voltages on 1.2 V and 1.8 V pins. See
Table 2, Recommended Operating Conditions and Table 6, DC Characteristics.
• Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is
not used then an external pull-down resistor is required.
• Corrected the FLSH_SO/LAN_DISABLE signal definition. If Flash functionality is
not used then an external pull-up resistor is required.
• Removed note “b” from Table 2 and note “a” from Tables 3 and 4.
• Moved the note following Table 5 before Table 3.
• Replace Intel logo, updated the Product Features title page, and document order-
ing information.
• Updated Section 3.3. Removed the internal pullup device text from the FLASH
Serial Data Output / LAN Disable pin description.
Oct 2002
July 2003
Oct 2004
1.0
1.5
2.0
Nov 2004
2.1
Jan 2005
Apr 2005
June 2006
Aug 2006
Aug 2007
Dec 2007
2.2
2.3
2.4
2.5
2.6
2.7
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82541 Family of Gigabit Ethernet Controllers may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-
296-9333
Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © 2007, Intel Corporation.
* Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without
intent to infringe.
Networking Silicon — 82541(PI/GI/EI)
Contents
1.0
Introduction......................................................................................................................... 7
1.1
1.2
1.3
2.0
2.1
2.2
2.3
2.4
3.0
3.1
3.2
Document Scope................................................................................................... 7
Reference Documents...........................................................................................8
Product Codes....................................................................................................... 8
External Architecture Block Diagram...................................................................11
Internal MAC Architecture Block Diagram...........................................................12
Integrated 10/100/1000Mbps PHY ......................................................................12
System Interface .................................................................................................12
Signal Type Definitions........................................................................................11
PCI Bus Interface Signals (56) ............................................................................11
3.2.1 PCI Address, Data and Control Signals (44) ..........................................12
3.2.2 Arbitration Signals (2).............................................................................13
3.2.3 Interrupt Signal (1)..................................................................................13
3.2.4 System Signals (4) .................................................................................13
3.2.5 Error Reporting Signals (2).....................................................................14
3.2.6 Power Management Signals (3) .............................................................14
3.2.7 SMB Signals (3) .....................................................................................14
EEPROM and Serial FLASH Interface Signals (9)..............................................15
Miscellaneous Signals.........................................................................................15
3.4.1 LED Signals (4) ......................................................................................15
3.4.2 Other Signals (4) ....................................................................................16
PHY Signals ........................................................................................................16
3.5.1 Crystal Signals (2) ..................................................................................16
3.5.2 Analog Signals (10) ................................................................................16
Test Interface Signals (6) ....................................................................................17
Power Supply Connections .................................................................................17
3.7.1 Digital and Analog Supplies ...................................................................17
3.7.2 Grounds, Reserved Pins and No Connects ...........................................18
3.7.3 Voltage Regulation Control Signals (2) ..................................................18
Absolute Maximum Ratings.................................................................................19
Targeted Recommended Operating Conditions..................................................19
4.2.1 General Operating Conditions................................................................19
4.2.2 Voltage Ramp and Sequencing Recommendations...............................20
DC Specifications ................................................................................................22
AC Characteristics...............................................................................................25
Timing Specifications ..........................................................................................27
Package Information ...........................................................................................33
Thermal Specifications ........................................................................................35
Pinout Information ...............................................................................................36
Architectural Overview .....................................................................................................11
Signal Descriptions...........................................................................................................11
3.3
3.4
3.5
3.6
3.7
4.0
Voltage, Temperature, and Timing Specifications............................................................19
4.1
4.2
4.3
4.4
4.5
5.0
5.1
5.2
5.3
Package and Pinout Information ......................................................................................33
iii
82541(PI/GI/EI) — Networking Silicon
5.4
Visual Pin Assignments....................................................................................... 46
Figures
1
2
3
4
5
6
7
8
9
10
11
11
12
13
82541(PI/GI/EI) External Architecture Block Diagram ........................................ 11
Internal Architecture Block Diagram.................................................................... 12
AC Test Loads for General Output Pins.............................................................. 27
AC Test Loads for General Output Pins.............................................................. 28
AC Test Loads for General Output Pins.............................................................. 29
AC Test Loads for General Output Pins.............................................................. 29
TVAL (max) Rising Edge Test Load.................................................................... 30
TVAL (max) Falling Edge Test Load ................................................................... 30
TVAL (min) Test Load ......................................................................................... 30
TVAL Test Load (PCI 5 V Signaling Environment) ............................................. 31
Link Interface Rise/Fall Timing............................................................................ 31
82541(PI/GI/EI) Mechanical Specifications......................................................... 33
196 PBGA Package Pad Detail........................................................................... 34
Visual Pin Assignments....................................................................................... 46
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
13
14
15
16
17
18
19
20
Absolute Maximum Ratings ................................................................................ 19
Recommended Operating Conditions ................................................................ 19
3.3V Supply Voltage Ramp ................................................................................. 20
1.8V Supply Voltage Ramp ................................................................................. 20
1.2V Supply Voltage Ramp ................................................................................. 21
DC Characteristics .............................................................................................. 22
Power Specifications - D0a ................................................................................. 22
Power Specifications - D3cold ............................................................................ 23
Power Specifications D(r) Uninitialized ............................................................... 23
Power Specifications - Complete Subsystem ..................................................... 24
I/O Characteristics............................................................................................... 24
AC Characteristics: 3.3 V Interfacing .................................................................. 25
25 MHz Clock Input Requirements ..................................................................... 25
Reference Crystal Specification Requirements................................................... 26
Link Interface Clock Requirements ..................................................................... 26
EEPROM Interface Clock Requirements ............................................................ 26
PCI Bus Interface Clock Parameters .................................................................. 27
PCI Bus Interface Timing Parameters................................................................. 28
PCI Bus Interface Timing Measurement Conditions ........................................... 29
Link Interface Rise and Fall Times...................................................................... 31
EEPROM Link Interface Clock Requirements..................................................... 32
EEPROM Link Interface Clock Requirements..................................................... 32
Thermal Characteristics ...................................................................................... 35
PCI Address, Data and Control Signals .............................................................. 36
PCI Arbitration Signals ........................................................................................ 36
Interrupt Signals .................................................................................................. 36
System Signals ................................................................................................... 36
Error Reporting Signals....................................................................................... 37
Power Management Signals ............................................................................... 37
SMB Signals........................................................................................................ 37
iv
Networking Silicon — 82541(PI/GI/EI)
21
22
23
24
25
26
27
28
29
30
31
32
Serial EEPROM Interface Signals.......................................................................37
Serial FLASH Interface Signals...........................................................................37
LED Signals.........................................................................................................37
Other Signals.......................................................................................................38
IEEE Test Signals ...............................................................................................38
PHY Signals ........................................................................................................38
Test Interface Signals..........................................................................................38
Digital Power Signals ..........................................................................................38
Analog Power Signals .........................................................................................39
Grounds and No Connect Signals.......................................................................39
Voltage Regulation Control Signals.....................................................................39
Signal Names in Pin Order..................................................................................40
v
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