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Datasheet> 器件分类 > 模拟混合信号IC> 放大器电路> SMP04GBC
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SMP04GBC

产品描述CMOS Quad Sample-and-Hold Amplifier
产品类别模拟混合信号IC    放大器电路   
文件大小487KB，共15页
制造商ADI(亚德诺半导体)
官网地址https://www.analog.com
标准
下载文档 详细参数 选型对比 全文预览

SMP04GBC概述

CMOS Quad Sample-and-Hold Amplifier

SMP04GBC规格参数

参数名称属性值
Brand NameAnalog Devices Inc
是否无铅含铅
是否Rohs认证符合
parentfamilyid1207364
厂商名称ADI(亚德诺半导体)
Objectid1522559115
零件包装代码DIE
包装说明DIE,
针数0
Reach Compliance Codecompliant
ECCN代码EAR99
compound_id5000957
最长采集时间11 µs
标称采集时间3.6 µs
放大器类型SAMPLE AND HOLD CIRCUIT
最大模拟输入电压7.5 V
最小模拟输入电压-7.5 V
最大下降率0.025 V/s
JESD-30 代码R-XUUC-N15
负供电电压上限
标称负供电电压 (Vsup)
功能数量4
端子数量15
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料UNSPECIFIED
封装代码DIE
封装形状RECTANGULAR
封装形式UNCASED CHIP
峰值回流温度（摄氏度）NOT SPECIFIED
认证状态Not Qualified
采样并保持/跟踪并保持SAMPLE
供电电压上限17 V
标称供电电压 (Vsup)12 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式NO LEAD
端子位置UPPER
处于峰值回流温度下的最长时间NOT SPECIFIED

SMP04GBC文档预览

SMP04–SPECIFICATIONS
(@ V
DD
= +12.0 V, V
SS
= DGND = 0 V, R
L
= No Load, T
A
= Operating Temperature Range
specified in Absolute Maximum Ratings, unless otherwise noted.)
Parameter
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
1
Output Sink Current
1
Output Voltage Range
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
Acquisition Time
3
Acquisition Time
3
Hold Mode Settling Time
Slew Rate
4
Capacitive Load Stability
Analog Crosstalk
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
2
ELECTRICAL CHARACTERISTICS
Symbol
V
OS
V
HS
∆V/∆t
I
SOURCE
I
SINK
OVR
Conditions
V
IN
= 6 V
V
IN
= 6 V, T
A
= +25°C to +85°C
V
IN
= 6 V, T
A
= –40°C
V
IN
= 6 V, T
A
= +25°C
V
IN
= 6 V
V
IN
= 6 V
R
L
= 20 kΩ
R
L
= 10 kΩ
Min
–10
Typ
0.01
±
2.5
2.5
2
Max
+10
4
5
25
10.0
9.5
Units
%
mV
mV
mV
mV/s
mA
mA
V
V
V
V
µA
µs
µs
µs
µs
V/µs
pF
dB
dB
mA
mW
1.2
0.5
0.06
0.06
2.4
0.5
V
INH
V
INL
I
IN
t
AQ
t
AQ
t
H
SR
C
L
T
A
= +25°C, 0 V to 10 V Step to 0.1%
–40°C
≤
T
A
≤
+85°C
T
A
= +25°C, 0 V to 10 V Step to 0.01%
To 1 mV
R
L
= 20 kΩ
<30% Overshoot
0 V to 10 V Step
10.8 V
≤
V
DD
≤
13.2 V
0.8
1
4.25
5.25
3
3.5
3.75
9
1
4
500
–80
75
4
PSRR
I
DD
P
DIS
60
7
84
= +5.0 V, V
SS
= –5.0 V, DGND = 0.0 V, R
L
= No Load, T
A
= Operating Temperature
Range specified in Absolute Maximum Ratings, unless otherwise noted.)
DD
ELECTRICAL CHARACTERISTICS
(@ V
Parameter
Symbol
V
OS
V
HS
∆V/∆t
R
OUT
I
SOURCE
I
SINK
OVR
V
INH
V
INL
I
IN
t
AQ
t
AQ
t
H
SR
C
L
PSRR
I
DD
P
DIS
Conditions
V
IN
= 0 V
V
IN
= 0 V, T
A
= +25°C to +85°C
V
IN
= 0 V, T
A
= –40°C
V
IN
= 0 V, T
A
= +25°C
V
IN
= 0 V
V
IN
= 0 V
R
L
= 20 kΩ
Min
–10
Typ
0.01
±
2.5
2.5
2
1
Max
+10
4
5
25
Units
%
mV
mV
mV
mV/s
Ω
mA
mA
V
V
V
µA
µs
µs
µs
V/µs
pF
dB
mA
mW
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Resistance
Output Source Current
1
Output Sink Current
1
Output Voltage Range
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
Acquisition Time
3
Acquisition Time
3
Hold Mode Settling Time
Slew Rate
5
Capacitive Load Stability
2
1.2
0.5
–3.0
2.4
0.5
+3.0
0.8
1
11
–3 V to +3 V Step to 0.1%
–3 V to +3 V Step to 0.01%
To 1 mV
R
L
= 20 kΩ
<30% Overshoot
±
5 V
≤
V
DD
≤ ±
6 V
3.6
9
1
3
500
60
75
3.5
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
5.5
55
NOTES
1
Outputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels.
2
All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3
This parameter is guaranteed without test.
4
Slew rate is measured in the sample mode with a 0 V to 10 V step from 20% to 80%.
5
Slew rate is measured in the sample mode with a –3 V to +3 V step from 20% to 80%.
Specifications are subject to change without notice.
–2–
REV. D
SMP04
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
Package Type
16-Lead Cerdip
16-Lead Plastic DIP
16-Lead SO
*
JA
JA
*
JC
Units
°C/W
°C/W
°C/W
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V, 17 V
V
LOGIC
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
V
IN
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
V
OUT
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
(Not Short-Circuit Protected)
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+ 0.3 V
Operating Temperature Range
EQ, EP, ES . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
94
76
92
12
33
27
is specified for worst case mounting conditions, i.e.,
JA
is specified for device
in socket for cerdip and plastic DIP packages;
JA
is specified for device soldered
to printed circuit board for SO package.
CAUTION
1. Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; function operation
at or above this specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device reliability.
2. Digital inputs and outputs are protected; however, permanent damage may
occur on unprotected units from high energy electrostatic fields. Keep units in
conductive foam or packaging at all times until ready to use. Use proper antistatic
handling procedures.
3. Remove power before inserting or removing units from their sockets.
PIN CONNECTIONS
16-Lead Cerdip
16-Lead Plastic DIP
16-Lead SO
V
OUT2
1
V
OUT1
2
V
IN1
3
NC 4
16 V
DD
15 V
OUT3
14 V
OUT4
ORDERING GUIDE
Model
SMP04EQ
SMP04EP
SMP04ES
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Description
Cerdip-16
PDIP-16
SO-16
Package
Options*
Q-16
N-16
R-16A
13 V
SS
TOP VIEW
V
IN2
5 (Not to Scale) 12 V
IN4
S/H
1
6
S/H
2
7
DGND 8
11 V
IN3
10
S/H
4
9
S/H
3
SMP04
*Q = Cerdip; N = Plastic DIP; R = Small Outline.
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP04 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
SMP04
V
OUT1
V
OUT2
V
DD
V
OUT3
V
OUT4
V
IN1
V
IN2
V
SS
V
IN4
V
IN3
S/H
1
S/H
2
DGND
S/H
3
S/H
4
Dice Characteristics
Die Size: 0.80 x 0.120 mil = 9,600 sq. mil
(2.032 x 3.048mm = 6.193 sq. mm)
WAFER TEST LIMITS
Parameter
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
(@ V
DD
= +12 V, V
SS
= DGND = 0 V, R
L
= No Load, T
A
= +25 C, unless otherwise noted.)
Symbol
V
OS
V
HS
∆V/∆t
I
SOURCE
I
SINK
OVR
Conditions
V
IN
= +6 V
V
IN
= +6 V
V
IN
= +6 V
V
IN
= +6 V
V
IN
= +6 V
R
L
= 20 kΩ
R
L
= 10 kΩ
SMP04G
Limits
±
10
±
4
25
1.2
0.5
0.06/10.0
0.06/9.5
2.4
0.8
1
10.8 V
≤
V
DD
≤
13.2 V
60
7
84
Units
mV max
mV max
mV/s max
mA min
mA min
V min/max
V min/max
V min
V max
µA
max
dB min
mA max
mW max
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
V
INH
V
INL
I
IN
PSRR
I
DD
P
DIS
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
–4–
REV. D
Typical Performance Characteristics–SMP04
10000
V
DD
= +12V
V
SS
= 0V
V
IN
= +5V
R
L
= 10k
5
V
DD
= +12V
V
SS
= 0V
3
1800
1600
V
DD
= +12V
V
SS
= 0V
DROOP RATE – mV/s
DROOP RATE – mV/s
DROOP RATE – mV/s
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
1000
1400
1
0
–1
100
1200
1000
10
–3
800
600
0
1
2
3 4
5
6 7
8
INPUT VOLTAGE – Volts
9
10
0
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE – C
–5
Figure 1. Droop Rate vs. Temperature
Figure 2. Droop Rate vs. Input
Voltage (T
A
= +25
°
C)
Figure 3. Droop Rate vs. Input
Voltage (T
A
= +125
°
C)
3
2
T
A
= +25 C
V
DD
= +12V
V
SS
= 0V
HOLD STEP – mV
3
2
7
V
DD
= +12V
V
SS
= 0V
V
IN
= +5V
T
A
= +25 C
V
SS
= 0V
6
1
1
SLEW RATE – V/ s
HOLD STEP – mV
0
–SR
5
0
–1
–1
+SR
4
–2
–3
0
1
2
3
4
5
6
7 8
INPUT VOLTAGE – Volts
9
10
–2
–3
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE – C
3
10
11
12
13 14
15
V
DD
– Volts
16
17
18
Figure 4. Hold Step vs. Input Voltage
Figure 5. Hold Step vs. Temperature
Figure 6. Slew Rate vs. V
DD
2
1
V
DD
= +12V
V
SS
= 0V
OFFSET VOLTAGE – mV
20
15
10
5
0
–5
–10
R
L
= 10k
–15
–20
R
L
=
V
DD
= +12V
V
SS
= 0V
4
2
V
DD
= +12V
V
SS
= 0V
R
L
=
0
R
L
= 20k
–2
–4
–6
–8
–10
0
1
2
3
4
5
6
7 8
INPUT VOLTAGE – Volts
9
10
0
1
2
3 4
5
6
7 8
INPUT VOLTAGE – Volts
9
10
R
L
= 10k
OFFSET VOLTAGE – mV
0
R
L
=
R
L
= 20k
R
L
= 20k
–1
–2
R
L
= 10k
–3
–4
0
1
2
3 4
5
6 7
8
INPUT VOLTAGE – Volts
9
10
Figure 7. Offset Voltage vs. Input
Voltage (T
A
= +25
°
C)
Figure 8. Offset Voltage vs. Input
Voltage (T
A
= +125
°
C)
REV. D
–5–
OFFSET VOLTAGE – mV
Figure 9. Offset Voltage vs. Input
Voltage (T
A
= –55
°
C)
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SMP04GBC相似产品对比

SMP04GBC SMP04AQ/883 SMP04G SMP04EBIP SMP04EBIQ SMP04EBIS
描述 CMOS Quad Sample-and-Hold Amplifier IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 9 us ACQUISITION TIME, CDIP16, HERMETIC SEALED, CERDIP-16, Sample and Hold Circuit IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, UUC16, Sample and Hold Circuit IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 9 us ACQUISITION TIME, PDIP16, PLASTIC, DIP-16, Sample and Hold Circuit IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 9 us ACQUISITION TIME, CDIP16, HERMETIC SEALED, CERDIP-16, Sample and Hold Circuit IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 9 us ACQUISITION TIME, PDSO16, SOIC-16, Sample and Hold Circuit
是否Rohs认证 符合 不符合 不符合 不符合 不符合 不符合
厂商名称 ADI(亚德诺半导体) ADI(亚德诺半导体) ADI(亚德诺半导体) ADI(亚德诺半导体) ADI(亚德诺半导体) ADI(亚德诺半导体)
零件包装代码 DIE DIP WAFER DIP DIP SOIC
针数 - 16 16 16 16 16
Reach Compliance Code compliant unknown compliant compliant compliant compliant
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
放大器类型 SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT
最大模拟输入电压 7.5 V 3 V 17 V 3 V 3 V 3 V
最小模拟输入电压 -7.5 V -3 V -17 V -3 V -3 V -3 V
最大下降率 0.025 V/s 0.025 V/s 0.025 V/s 0.025 V/s 0.025 V/s 0.025 V/s
JESD-30 代码 R-XUUC-N15 R-GDIP-T16 X-XUUC-N16 R-PDIP-T16 R-GDIP-T16 R-PDSO-G16
负供电电压上限 - -8.5 V -17 V -8.5 V -8.5 V -8.5 V
功能数量 4 4 4 4 4 4
端子数量 15 16 16 16 16 16
封装主体材料 UNSPECIFIED CERAMIC, GLASS-SEALED UNSPECIFIED PLASTIC/EPOXY CERAMIC, GLASS-SEALED PLASTIC/EPOXY
封装代码 DIE DIP DIE DIP DIP SOP
封装形状 RECTANGULAR RECTANGULAR UNSPECIFIED RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 UNCASED CHIP IN-LINE UNCASED CHIP IN-LINE IN-LINE SMALL OUTLINE
峰值回流温度（摄氏度） NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
采样并保持/跟踪并保持 SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE
供电电压上限 17 V 8.5 V 17 V 8.5 V 8.5 V 8.5 V
标称供电电压 (Vsup) 12 V 5 V 12 V 5 V 5 V 5 V
表面贴装 YES NO YES NO NO YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS
端子形式 NO LEAD THROUGH-HOLE NO LEAD THROUGH-HOLE THROUGH-HOLE GULL WING
端子位置 UPPER DUAL UPPER DUAL DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
包装说明 DIE, HERMETIC SEALED, CERDIP-16 - PLASTIC, DIP-16 HERMETIC SEALED, CERDIP-16 SOIC-16
标称采集时间 3.6 µs 9 µs - 9 µs 9 µs 9 µs
标称负供电电压 (Vsup) - -5 V - -5 V -5 V -5 V
最高工作温度 85 °C 125 °C - 85 °C 85 °C 85 °C
最低工作温度 -40 °C -55 °C - -40 °C -40 °C -40 °C
温度等级 INDUSTRIAL MILITARY - INDUSTRIAL INDUSTRIAL INDUSTRIAL
JESD-609代码 - e0 e0 e0 e0 e0
长度 - 19.05 mm - 20.13 mm 19.05 mm 10.3 mm
座面最大高度 - 5.08 mm - 5.33 mm 5.08 mm 2.65 mm
最大压摆率 - 5.5 mA 7 mA 5.5 mA 5.5 mA 5.5 mA
端子面层 - Tin/Lead (Sn/Pb) TIN LEAD TIN LEAD TIN LEAD TIN LEAD
端子节距 - 2.54 mm - 2.54 mm 2.54 mm 1.27 mm
宽度 - 7.62 mm - 7.62 mm 7.62 mm 7.5 mm

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阻抗匹配有烦恼？帮您揭秘（上）
现在的所有努力，都只为靠近你，因为你就是我的50欧姆点这是一句射频情话，你懂这句情话背后的深意吗？今天，就过来为你详细揭秘。一、 阻抗匹配电路的作用 阻抗控制在硬件设计中是一个比较重 ......
alan000345 无线连接
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