256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
Features
Synchronous DRAM Module
MT8LSDT3264A(I) - 256MB
MT16LSDT6464A(I) - 512MB
For the latest data sheet, please refer to the Micron
®
Web site:
www.micron.com/products/modules
Features
• PC100- and PC133-compliant
• 168-pin, dual in-line memory module (DIMM)
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Unbuffered
• 256MB (32 Meg x 64), 512MB (64 Meg x 64)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, including Concurrent Auto
Precharge, and Auto Refresh Modes
• 64ms, 8,192 cycle Auto Refresh cycle
• Self Refresh Mode
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
Table 1:
Module
Marking
-13E
-133
-10E
Figure 1:
168-Pin DIMM (MO–161)
Low Profile 1.125in. (28.575mm)
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
• Memory Clock/CAS Latency
(133 MHz)/CL = 2
(133 MHz)/CL = 3
(100 MHz)/CL = 2
• PCB
Low profile 1.125in. (28.575mm)
Marking
G
Y
1
None
I
1, 2
-13E
-133
-10E
1
See page 2 note
Timing Parameters
Clock
Frequency
133 MHz
133 MHz
100 MHz
Access Time
CL = 2
5.4ns
–
9ns
CL = 3
–
5.4ns
7.5ns
Setup
Time
1.5
1.5
2ns
Hold
Time
0.8
0.8
1ns
Notes: 1. Consult Micron for product availability.
2. Industrial Temperature Option available in -
133 speed only.
Table 2:
Address Table
256MB
512MB
8K
4 (BA0, BA1)
256Mb (32 Meg x 8)
8K (A0–A12)
1K (A0–A9)
2 (S0,S2; S1,S3)
8K
4 (BA0, BA1)
256Mb (32 Meg x 8)
8K (A0–A12)
1K (A0–A9)
1 (S0,S2)
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 3:
Part Numbers
Module Density
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
Configuration
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
32 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
System Bus Speed
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
Part Number
MT8LSDT3264AG-13E_
MT8LSDT3264AY-13E_
MT8LSDT3264A(I))G-133_
MT8LSDT3264A(I)Y-133_
MT8LSDT3264AG-10E_
MT8LSDT3264AY-10E_
MT16LSDT6464AAG-13E_
MT16LSDT6464AY-13E_
MT16LSDT6464A(I)G-133_
MT16LSDT6464A(I)Y-133_
MT16LSDT6464AG-10E_
MT16LSDT6464AY-10E_
Note:
The designators for component and PCB revision are the last two characters of each part
number. Consult factory for current revision codes. Example: MT8LSDT3264AG-133D2.
Pin Assignments and Descriptions
Table 4:
Pin Assignment (168-Pin DIMM Front)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Symbol
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
NC
Pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
NC
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
S0#
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Symbol
V
SS
NC
S2#
DQMB2
DQMB3
NC
V
DD
NC
NC
NC
NC
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
NC
CKE1
Pin
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
NC
SDA
SCL
V
DD
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Assignment
(168-Pin DIMM Back)
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Symbol
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
NC
Pin
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Symbol
NC
V
SS
NC
NC
V
DD
CAS#
DQMB4
DQMB5
S1#
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CK1
A12
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
Symbol
V
SS
CKE0
S3#
DQMB6
DQMB7
NC
V
DD
NC
NC
NC
NC
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
NC
Pin
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
Figure 2:
Pin Locations (168-Pin DIMM)
Front View
U10
U1
U2
U3
U4
U6
U7
U8
U9
1.125 inches
28.57 millimeters
PIN 1
PIN 41
PIN 84
Back View (Populated only for dual rank, 512MB module)
U11
U12
U13
U14
U16
U17
U18
U19
PIN 168
PIN 125
PIN 85
Indicates a V
DD
pin
Indicates a V
SS
pin
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 6:
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 2 for for information
Pin Number
27, 111, 115
42, 79, 125, 163
Symbol
RAS#, CAS#,
WE#
CK0–CK3
Type
Input
Input
Description
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in
progress). CKE is synchronous except after the device enters
power- down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input
buffers, including CK, are disabled during power-down and
self refresh modes, providing low standby power.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto prcharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory arrary in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Data I/O: Data bus.
63, 128
CKE0, CKE1
Input
30, 45,114, 129
S0#–S3#
Input
28, 29, 46, 47, 112, 113, 130,
131
DQMB0–DQMB7
Input
39, 122
BA0, BA1
Input
33–38, 117–121, 123, 126
A0–A12
Input
83
165–167
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95, 97–101,
103–104, 139–142, 144,
149–151, 153–156,158–161
82
SCL
SA0–SA2
DQ0–DQ63
Input
Input
Input/
Output
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 6:
Pin Descriptions (Continued)
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 2 for for information
Pin Number
6, 18, 26, 40, 41, 49, 59, 73,
84, 90, 102, 110, 124, 133,
143, 157, 168
1, 12, 23, 32, 43, 54, 64, 68,
78, 85, 96, 107, 116, 127,
138, 148, 152, 162
21–22, 24–25, 31, 44, 48,
50–53, 61–62, 80, 81, 105–
106, 108–109, 132, 134–137,
145–147, 164
Symbol
V
DD
Type
Supply
Description
Power Supply: +3.3V ±0.3V.
V
SS
Supply
Ground.
NC
–
Not Connected: These pins are not connected on these
modules.
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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