SED1190
CMOS LCD 64-COMMON DRIVERS
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DESCRIPTION
The SED1190 is a dot matrix LCD common (row) driver for driving high-capacity LCD panel at duty cycles
higher than 1/64. The LSI uses two serially connected, 32-bit shift registers to hold the display data, and level
shifter converts the TTL level 64-bit parallel data from the shift registers to levels suitable for use by the LCD
drive circuitry. The SED1190 generates common drive signals using the voltages supplied to LCD drive
voltages pins.
The SED1190 is used in conjunction with the SED1180 (64-bit row driver) to drive a large capacity dot matrix
LCD panel.
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FEATURES
•
Low-power CMOS technology
•
64-bit common (row) driver
•
Display blanking
•
Duty cycle: 1/64 to 1/128
•
Daisy chain enable support
s
SYSTEM BLOCK DIAGRAM
•
Wide range of LCD voltage: –14V to –25V
•
Supply voltage: 5.0V
±10%
•
Package: ............................... QFP1-80 pin (F
QFP5-80 pin (F
0A
)
5A
)
DIE: Al pad chip (D
0A
)
D0 ~ D3
XSCL
LP, FR
YSCL
YD
LCD
CONTR
SED1180
64
SED1180
64
SED1180
64
SED1180F
64
SED1190
64
256SEG
×
64 COM
DUTY: 1/64
705
SED1190
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BLOCK DIAGRAM
0
COM
31
LAT
DI
INH
Latch
LCD Driver
Level Shifter
Shift Register
32 bits
32 bits
32 bits
Voltage Control
YSCL
Shift Register
Level Shifter
FR
5
V
SS
V
DD
V2
V3
V
SSH
32
COM
63
LCD Driver
32 bits
32 bits
32 bits
DO
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PIN CONFIGURATION
DO
V
SSH
V
4
NC
NC
NC
NC
V
1
V
SS
V
DD
NC
DI
LAT
INH
FR
YSCL
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
60
55
50
45
65
40
70
35
SED1190
75
Index
30
80
1
5
10
15
20
25
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
706
SED1190
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
Number
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
COM11
COM10
COM 9
COM 8
COM 7
COM 6
COM 5
COM 4
COM 3
COM 2
COM 1
COM 0
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
Number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
Number
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
COM60
COM61
COM62
COM63
DO
V
SSH
V4
NC
NC
NC
NC
V1
V
SS
V
DD
NC
DI
LAT
INH
FR
YSCL
NC = Not connected
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PIN DESCRIPTION
Pin Name
COM0 to COM63
DI
LCD common drive outputs
Serial data input
Transparent latch control input:
LAT
LAT
H
L
DO
YSCL
FR
INH
V
DD
, V
SS
V1, V4, V
SSH
Serial data output
Serial data shift clock. Data is shifted through the controller on the falling
edge of this clock
LCD AC-drive signal input
Active-low blanking input
Logic power supply inputs
LCD drive power inputs
V
DD
≥
V1
≥
V4
≥
V
SSH
DI
H
L
X
DI latch output
H
L
DI latch
Function
707
SED1190
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
•
Parameter
Supply voltage (1)
Supply voltage (2)
Input voltage
Operating temperature
Storage temperature
Soldering temperature and time
Notes:
1. All voltages referenced to a V
DD
of 0 V.
Symbol
V
SS
V
SSH
V1, V4
V
I
T
opr
T
stg
T
sol
Ratings
–7.0 to +0.3
–28.0 to +0.3
V
SS
–0.3 to +0.3
–20 to +75
–55 to +125
260, 10
Unit
V
V
V
°C
°C
°C,
s
2. V1 and V4 must satisfy the relationship V
DD
≥
V1, V4
≥
V
SSH
3. Exceeding the absolute maximum ratings can cause permanent damage to the device. Functional operation under these
conditions is not implied.
4. Moisture resistance of flat packages can be reduced by the soldering process. Care should be taken to avoid thermally
stressing the package during board assembly.
708
SED1190
•
DC Characteristics
Parameter
Supply voltage (1)
Symbol
V
SS
V1
V4
V
SSH
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
Shift clock
Frame signal
Input capacitance
Common output on
resistance
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
YSCL
FR
C
I
R
COM
(V
DD
= 0V, V
SS
= –5.0 V
±10%,
T
a
= –20 to 75°C)
Conditions
Rating
Unit
Min
Typ
Max
–5.5
–5.0
–4.5
V
V
SSH
—
V
DD
V
V
SSH
—
V
DD
V
–25.0
—
–14.0
V
–25.0
—
–5.0
V
0.2V
SS
— V
DD
+0.3
V
V
SS
–0.3
—
0.8V
SS
V
–0.4
—
—
V
—
—
V
SS
+0.4
V
—
0.05
2.0
µA
—
0.05
5.0
µA
—
—
2.5
MHz
—
1/60
—
s
—
5.0
8.0
pF
—
0.8
1.0
—
0.9
1.3
kΩ
—
1.3
2.0
—
3.0
30.0
—
0.05
30
µA
Supply voltage (2)
Recommended V
SSH
Operable V
SSH
(see note)
I
OH
= –0.6 mA
I
OL
= 0.6 mA
0 V
≥
V
I
≥
V
SS
0 V
≥
V
O
≥
V
SS
T
a
= 25°C
V
OH
= V
DD
–0.5 V
V
OL
= V
SSH
+0.5 V
COM bit
SED
1190
V
SSH
= –20.0 V
V
SSH
= –14.0 V
V
SSH
= –9.0 V
V
SSH
= –5.0 V
V
SSH
= –25 V, V
SSH
= –5.5 V,
V
I
= V
DD
Quiescent current
I
Q
Operating current for
the logic
I
SS
Operating current for LCD
I
SSH
Pull up MOS current
–I
p
V
SS
= –5.0 V,
V
IH
= V
DD
,
V
IL
= V
SS
,
YSCL cycle =
FR cycle = 16.7 ms 130
µs
(duty 50%), All
“H” output
terminals are
opened at every
data input all
1/128 duty.
V
SS
= –4.5 V,
V
1
= –2.0 V,
V
4
= –18.0 V,
YSCL cycle =
FR cycle = 16.7 ms 130
µs
(duty 50%), All
“H” output
terminals are
opened at every
data input of
1/128 duty.
V
SS
= –5.0 V, V
IL
= –5.0 V
Applicable to LAT input terminals
—
3.0
8.0
µA
—
3.0
8.0
µA
10.0
25.0
50.0
µA
Note:
Error free operation is guaranteed in this range but the output resistance of the LCD drivers is higher than in the recommended
operating range. It is suggested that the driver is tested with the target LCD panel to determine if performance is acceptable.
709
FPGA/CPLD
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