512 MByte/ 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Industrial Grade
Fact Sheet
FEATURES:
• Industry Standard ATA/IDE Bus Interface
– Host Interface: 16-bit access
– Supports up to PIO Mode-6
– Supports up to Multi-word DMA Mode-4
– Supports up to Ultra DMA Mode-4
• Low Power, 3.3V Power Supply
• 5.0V or 3.3V Host Interface Through V
DDQ
Pins
• Low Current Operation:
– Active mode: 85 mA Typical
– Sleep mode: 160 µA Typical
• Power Management Unit
– Immediate disabling of unused circuitry without host
intervention
– Zero wake-up latency
• Expanded Data Protection
– WP#/PD# pin configurable by firmware for
prevention of data overwrites
• 20-byte Unique ID for Enhanced Security
– Factory Pre-programmed 10-byte Unique ID
– User-Programmable 10-byte ID
• Integrated Voltage Detector
– Prevents data loss due to unexpected power-down
or brownout.
• Endurance
– 100K cycles
• Data Retention
– 10 years
• Pre-programmed Embedded Firmware
– Executes industry standard ATA/IDE commands
– Implements dynamic wear-leveling algorithms to
substantially increase the longevity of flash media
– Embedded Flash File System
• Robust Built-in ECC
• Multi-tasking Technology Enables Fast
Sustained Write Performance (Host-to-Flash)
– Up to 20 MByte/sec
• Fast Sustained Read Performance (Flash-to-Host)
– Up to 30 MByte/sec
• Industrial Temperature Range
– -40°C to +85°C for industrial operation
• LBGA package
– 12mm x 24mm
• All non-Pb (lead-free) Devices are RoHS Compliant
PRODUCT DESCRIPTION
The
SST85LD0512,
SST85LD1001T
and
SST85LD1002U NANDrive™ integrated circuits (IC) are
high-performance, fully-integrated, embedded flash solid
state drives. They combine an integrated ATA Controller
and either 512 MByte, 1 GByte, or 2 GByte of NAND Flash
in a multi-chip package. These products are ideal for
industrial grade solid state mass storage applications
offering new and expanded functionality while enabling
cost effective designs.
The SST85LD0512 / SST85LD1001T / SST85LD1002U
NANDrives provide complete IDE Hard Disk Drive
functionality and compatibility in a 12mm x 24mm BGA
package for easy, space saving mounting to a system
motherboard. It is a perfect solution for portable, consumer
electronic products requiring smaller and more reliable data
storage.
The NANDrive provides a WP#/PD# pin to protect critical
information stored in the flash media from unauthorized
overwrites.
The NANDrive is pre-programmed with a 10-byte unique
serial ID. For even greater system security, the user has the
option of programming an additional 10 Bytes of ID space
to create a unique, 20-byte ID.
ATA-based solid state mass storage technology is widely
used in portable and desktop computers, digital
cameras, music players, handheld data collection
scanners, cellular phones, PCS phones, PDAs, handy
terminals, personal communicators, robotics, audio
recorders, monitoring devices, and set-top boxes.
SST NANDrive is a single device, solid state drive
designed for embedded ATA/IDE protocol systems and
supports standard ATA/IDE protocol with up to PIO Mode-
6, Multi-word DMA Mode-4 and Ultra DMA Mode-4
interface. The built in microcontroller and file management
firmware communicates with ATA standard interfaces;
thereby eliminating the need for additional or proprietary
software such as Flash File System (FFS) and Memory
Technology Driver (MTD) software.
©2008 Silicon Storage Technology, Inc.
S71382(01)-00-000
02/08
1
The SST logo, NANDrive, and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Some content is reproduced from the Com-
pactFlash Specification (2.0) by permission of the CompactFlash Association. Other content is reproduced from the ATA/ATAPI-6 (T13/1410D revision
3b) specification by permission of the National Committee for Information Technology Standards. These specifications are subject to change without
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Fact Sheet
1.0 GENERAL DESCRIPTION
Each NANDrive contains an integrated ATA Controller and
one or more NAND Flash dice in a LBGA package. Refer
to Figure 2-1 for the NANDrive block diagram.
1.1 Performance-optimized NANDrive
The heart of the NANDrive is the ATA Flash Disk Controller
which translates standard ATA signals into flash media data
and control signals. The following components contribute to
the NANDrive’s operation.
1.1.1 Microcontroller Unit (MCU)
The MCU translates ATA/IDE commands into data and
control signals required for flash media operation.
1.1.2 Internal Direct Memory Access (DMA)
The NANDrive uses internal DMA allowing instant data
transfer from buffer to flash media. This implementation
eliminates microcontroller overhead associated with the
traditional, firmware-based approach, thereby increasing
the data transfer rate.
1.1.3 Power Management Unit (PMU)
The power management unit controls the power
consumption of the NANDrive. The PMU dramatically
reduces the power consumption of the NANDrive by
putting the part of the circuitry that is not in operation into
sleep mode.
1.1.4 SRAM Buffer
A key contributor to the NANDrive performance is an
SRAM buffer. The buffer optimizes the host’s data transfer
to and from the flash media.
1.1.5 Embedded Flash File System
The embedded flash file system is an integral part of the
NANDrive. It contains MCU firmware that performs the
following tasks:
1. Translates host side signals into flash media
writes and reads.
2. Provides dynamic flash media wear leveling to
spread the flash writes to increase the longevity of
flash media.
3. Keeps track of data file structures.
4. Manages system security for the selected
protection zones.
©2008 Silicon Storage Technology, Inc.
S71382(01)-00-000
02/08
2
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Fact Sheet
1.1.6 Error Correction Code (ECC)
High performance is achieved through optimized hardware
error detection and correction.
1.1.7 Serial Communication Interface (SCI)
The Serial Communication Interface (SCI) is designed for
manufacturing error reporting. Always provide SCI interface
access to PCB design to aid in design validation.
1.1.8 Multi-tasking Interface
The multi-tasking interface enables fast, sustained write
performance by allowing concurrent Read, Program, and
Erase operations to multiple flash media devices.
1.2 NAND Flash
The NANDrive family utilize standard NAND Flash for data
storage.
2.0 FUNCTIONAL BLOCKS
NANDrive
ATA Flash Disk Controller
Embedded
Flash
File System
SRAM Buffer
MCU
Multi-tasking Interface
HOST
ATA/IDE
BUS
ECC
Internal
DMA
PMU
SCI
NAND
Flash
External
Flash
Media
Bus
FIGURE
2-1: NANDrive Block Diagram
1382 B1.0
©2008 Silicon Storage Technology, Inc.
S71382(01)-00-000
02/08
3
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Fact Sheet
3.0 PIN ASSIGNMENTS
The signal/pin assignments are listed in Table 3-1. Low
active signals have a “#” suffix. Pin types are Input, Output,
or Input/Output. Signals whose source is the host are
designated as inputs while signals that the NANDrive
sources are outputs.
The NANDrive functions in ATA mode, which is compatible
with IDE hard disk drives.
TOP VIEW (balls facing down)
10
NC
NC
DNU
DNU
9
NC
NC
DASP#
V
DD
D11
D14
IOWR#
V
SS
PDIAG# CSEL
V
DDQ
FAD7
DNU
DNU
8
SCID
OUT
D9
D10
D13
D15
IOCS16#
A2
CS3FX# FAD15
FAD6
7
SCID
IN
SCICLK
D8
V
SS
D12
POR#
V
SS
FAD13 FAD14
FAD5
6
FALE FCE4# WP#/PD# GND
V
SS
FAD12
FAD11 FAD4
5
FRE#
DNU
FCE6# FCE5#
V
DD
V
DD
FAD10 FAD3
4
FCLE RESET#
D7
D3
V
SS
D2
D6
D4
IORDY
DMARQ
V
SS
A1
FCE7#
FAD9
FAD2
FAD1
3
FWE#
D5
CS1FX# FAD8
2
NC
VREG
V
DDQ
D1
D0
IORD#
INTRQ DMACK
A0
V
DD
FAD0
NC
NC
1
NC
NC
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1319 91-lbz P1.2
FIGURE
3-1: Pin Assignments for 91-Ball LBGA
©2008 Silicon Storage Technology, Inc.
S71382(01)-00-000
02/08
4
512 MByte / 1 GByte / 2 GByte NANDrive
SST85LD0512 / SST85LD1001T / SST85LD1002U
Fact Sheet
TABLE
3-1: Pin Assignments (1 of 3)
Pin No.
Symbol
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DMACK
DMARQ
CS1FX#
CS3FX#
CSEL
91-
TFBGA
Pin
Type
I/O
Type
Name and Functions
Host Side Interface
K8
K3
L2
H8
G9
G8
H7
F9
F8
E8
F7
F4
H4
E3
H3
F3
G3
F2
G2
K2
J3
L3
L8
L9
I
O
I
I
I2U
O1
I2Z
I1U
DMA Acknowledge - input from host
DMA Request to host
CS1FX# is the chip select for the task file registers
CS3FX# is used to select the alternate status register and the Device Control register.
This internally pulled-up signal is used to configure this device as a Master or a Slave. When
this pin is grounded, this device is configured as a Master. When the pin is open, this device
is configured as a Slave. The pin setting should remain the same from Power-on to Power-
down.
IORD#: This is an I/O Read Strobe generated by the host. When
Ultra DMA mode is not active, this signal gates I/O data from the
device.
H2
HSTROBE
I
I2Z
HDMARDY#: In Ultra DMA mode when DMA Read is active, this signal is asserted by the
host to indicate that the host is ready to receive Ultra DMA data-in bursts. The host may
negate HDMARDY# to pause an Ultra DMA transfer.
HSTROBE: When DMA Write is active, this signal is the data-out strobe generated by the
host. Both the rising and falling edges of HSTROBE cause data to be latched by the device.
The host may stop generating HSTROBE edges to pause an Ultra DMA data-out burst.
This is an I/O Write Strobe generated by the host. When Ultra
DMA mode is not active, this signal is used to clock I/O data into
the device.
When Ultra DMA mode protocol is active, the assertion of this signal causes the termination
of the Ultra DMA burst
I/O
I1Z/O2
D[15:0] Data bus
I
I1Z
A[2:0] are used to select one of eight registers in the Task File.
IORD#
HDMARDY#
IOWR#
H9
STOP
I
I2Z
©2008 Silicon Storage Technology, Inc.
S71382(01)-00-000
02/08
5
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