16Mbit Enhanced SDRAM Family
4Mx4, 2Mx8, 1Mx16
Product Brief
Features
•
100% Pin, Function, and Timing Compatible with
JEDEC standard SDRAM
•
Integrated 8Kbit SRAM Row Cache
•
Synchronous Operation up to 150MHz
•
24ns Row Access Latency, 11ns Column Latency
•
Early Auto-Precharge
•
Programmable Burst Length (1, 2, 4, 8, full page)
•
Programmable CAS Latency (1, 2, 3)
•
•
•
•
•
•
Hidden Auto-Refresh without closing Read Pages
Low Power Suspend, Self-Refresh, and Power Down Modes
Optional No Write Transfer Mode
Single 3.3V Power Supply
Flexible V
DDQ
Supports LVTTL and 2.5V I/O
Packages: 44-pin TSOP-II (400 mils wide)
50-pin TSOP-II (400 mils wide)
Description
The Enhanced Memory Systems 16Mb enhanced
SDRAM (ESDRAM) family combines raw speed with
innovative architecture to optimize system price-
performance in high performance computer and
embedded control systems.
The ESDRAM is pin compatible with JEDEC standard
SDRAM. It is also function and timing compatible with
JEDEC standard SDRAM.
The two bank architecture combines 24ns DRAM arrays
with a 11ns SRAM row cache per bank. The ESDRAM is a
superset technology of JEDEC standard SDRAM. Its two
key functional features include early auto-precharge (close
DRAM page while burst reads are performed) and an
optional No Write Transfer mode. The ESDRAM is capable
of maintaining two open read pages and two open write
pages simultaneously via the No Write Transfer mode.
FUNCTIONAL BLOCK DIAGRAM
ADDRESS BUFFERS
ROW DECODER
BANK A
8Mbit
BANK B
8Mbit
A(11:0)
DATA LATCHES
SENSE AMPLIFIERS
SENSE AMPLIFIERS
SRAM ROW CACHE
COLUMN DECODER
SRAM ROW CACHE
COLUMN DECODER
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM(1:0)
COMMAND
DECODER
and
TIMING
GENERATOR
DATA LATCHES
DQ
Product
4Mx4
2Mx8
1Mx16
Cache Size
1Kx4
512x8
256x16
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product
without notice.
©
1999 Enhanced Memory Systems Inc.
1850 Ramtron Drive, Colorado Springs, CO 80921
Telephone
(800) 545-DRAM,
Fax
(719) 488-9095,
Web
http://www.edram.com
Rev. 2.4
16Mbit ESDRAM Family
Architecture
The ESDRAM architecture combines two banks of fast
24ns DRAM with two banks of 11ns SRAM row register
cache on one chip to improve memory latency. On a page
read miss, a DRAM bank is activated and data is
developed by the DRAM sense amplifiers in 13.3ns. The
sense amplifiers now hold an entire row of data (4K bits).
On a read command, the entire row is latched into the
SRAM row register and the specified starting address is
output in 11ns (CAS Latency 1 at clock frequencies up to
83MHz, and CAS Latency 2 up to 150MHz). The
architecture allows fast 11ns latency to any of the
constantly open rows on page hits.
Early auto-precharge can be performed since row data is
latched separately in the SRAM row cache from the
DRAM sense amplifiers. The precharge time can be
hidden behind a burst read from cache. This minimizes
subsequent page miss latency. The auto-precharge begins
one clock cycle after the Read-Autoprecharge command
and completes early enough to allow the next pipelined
random access to complete by the end of the current burst
cycle.
At 150MHz, all but one cycle of the next random access
to any location in the same bank can be hidden to increase
sustained bandwidth by up to two times over standard
SDRAM. For interleaved burst read accesses, the entire
precharge time is hidden and output data can be driven
without any wait states.
The ESDRAM architecture also offers the designer two
different cache load strategies via the mode register set for
write cycles. In Write Transfer mode, the row register
cache is always loaded with the sense amplifier contents
(DRAM row data) on a write command. This ensures
coherency between the row cache and the DRAM array.
This allows read-modify-write cycles and simplified
memory control logic.
In No Write Transfer mode, the row register caches are
not loaded during writes. Data is written to the DRAM
sense amplifiers and the prior row contents are maintained
in the row cache (for write page misses). If the on-chip
page hit/miss comparator determines that the write is to
the same row latched in the SRAM row cache, the write
updates the row cache as well as the DRAM sense
amplifiers to maintain coherency. No Write Transfer
mode allows immediate return to the prior cached read
page without otherwise incurring a page miss penalty.
Write page precharge and a bank activate times can be
hidden during cache reads.
The ESDRAM’s fast
precharge time minimizes latency between the end of a
write and the next read or write miss cycle. If a cache
read follows a write cycle, write precharge time can be
hidden.
The synchronous interface of the ESDRAM allows
operation at clock rates up to 150MHz with 2.5V I/O
levels. Fast input set-up and clock-to-output times allow
actual system operation at the specified clock rate.
Compatibility
By making the ESDRAM exactly pin-compatible with
JEDEC standard SDRAM, it is possible for the memory
controller to support both types of memory with a simple
mode selection.
Both SDRAM and ESDRAM use
identical memory footprints on the planar and identical
DIMM module wiring. Systems designed to support both
memory types can provide two distinct price/performance
points and a simple field upgrade with the ESDRAM.
1Mx16
PINOUTS
4Mx4
2Mx8
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
/WE
/CAS
/RAS
/CS
A11 (BS)
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VDD
NC
VSSQ
DQ0
VDDQ
NC
VSSQ
DQ1
VDDQ
NC
NC
/WE
/CAS
/RAS
/CS
VDD
DQ0
VSSQ
DQ1
VDDQ
DQ2
VSSQ
DQ3
VDDQ
NC
NC
/WE
/CAS
/RAS
/CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VSS
DQ7
VSSQ
DQ6
VDDQ
DQ5
VSSQ
DQ4
VDDQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
DQ3
VDDQ
NC
VSSQ
DQ2
VDDQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
44 pin TSOP-II
400 x 725 mils
0.8 mm pitch
50 pin TSOP-II
400 x 825 mils
0.8 mm pitch
A11 (BS) A11 (BS)
A10/AP A10/AP
A0
A0
A1
A2
A3
VDD
A1
A2
A3
VDD
2
Rev. 2.4
16Mbit ESDRAM Family
Basic Operating Modes
The ESDRAM operating modes are specified in the
following text and in the table below.
Hit and Miss Terminology -
“Hit” and “miss” refer to
whether or not a new row address presented to the
ESDRAM matches a row already activated in the device.
There are up to two rows or “pages” that can be open at
any given point in time. The row data or page contents
consist of 4096 bits and are held in each bank’s sense
amplifiers. Each page is selected by the bank select pin
A11 (BS). Each bank’s SRAM row cache is loaded only
when a read command is issued. The ESDRAM’s on-chip
row address comparator is used only in No Write Transfer
mode of operation.
The memory controller typically stores page (row)
address tags in order to determine which command to
issue based on the tag compare result.
Mode Register Set -
from pins A11 (BS) and
and /WE are low. The
the burst length, burst
transfer mode.
Two mode registers are loaded
A10-A0 when /CS, /RAS, /CAS,
standard mode register specifies
type, CAS latency, and write
Single Bank Precharge -
The ESDRAM will perform
a manual precharge of the bank specified by A11 (BS)
while A10/AP is low. Manual precharge terminates a
burst read after a delay equal to the CAS latency. It will
also terminate a burst write and mask data in the current
cycle.
Precharge All Banks -
The ESDRAM will precharge
both open banks if A10/AP is high. It will terminate burst
cycles exactly the same as the Single Bank Precharge
command.
Auto Refresh (CBR) -
The ESDRAM will perform an
internal refresh cycle on both DRAM banks. Both banks
must be closed before this command is executed. Unlike
standard SDRAM, this command can be executed while
performing cache burst reads. The contents of each row
cache are not lost during Auto Refresh cycles.
Self Refresh Entry -
The ESDRAM enters a self
refresh mode with refresh cycles automatically generated
by an internal clock. Self Refresh mode continues as long
as CKE is low. All input buffers except CKE are disabled.
The chip is in a low power standby mode.
Device Deselect -
When /CS is high, the command
decoder is disabled but the prior command will be
completed (i.e. a burst will complete).
Clock Suspend/Standby Mode -
When CKE is low,
the internal execution of the current command is
suspended until CKE returns high.
Power Down Entry/Exit -
If both DRAM banks are
precharged, CKE is low, and /CS is high, the chip will
enter its power down mode. Once the chip is in power
down mode, the chip will exit power down mode one clock
after CKE is returned high.
Data Write/Output Enable -
When DQM is low,
write data is written to the chip during a write command
and the output buffers are enabled during read commands.
DQM latency is two cycles for reads and zero cycles for
writes.
Data Mask/Output Disable -
When DQM is high,
write data is masked during a write command and the
output buffers are disabled during read commands. DQM
latency is two cycles for reads and zero cycles for writes.
Bank Activate -
A11 (BS) specifies one of the two
banks and the row address A10-A0 specifies which of the
2048 rows to load into its sense amplifiers. In No Write
Transfer mode, the ESDRAM compares the last row read
address to the current row address. If the two row
addresses match, a subsequent write updates the SRAM
row cache in addition to the DRAM. If the row addresses
do not match, only the DRAM is written.
Write -
The ESDRAM performs a write or burst write to
the bank specified by A11 (BS) and begins writing at the
start address specified by the column address A9-A0. If
the A10/AP pin is high, the auto-precharge operation
begins one cycle following the last write of the burst.
Note: In No Write Transfer mode, if the on-chip hit/miss
comparator result (from ACTV cycle) indicates a page hit,
then the write is performed to both the row cache and the
DRAM.
Read -
The ESDRAM loads the row cache and performs
a read or burst read from the cache to the bank specified
by A11 (BS) and begins reading at the start address
specified by the column address A9-A0. If the A10/AP
pin is high, the auto-precharge operation begins one cycle
following this command. The first read data is output
from the memory after the CAS latency (defined by the
Mode Register Set) has been satisfied.
Burst Terminate -
The ESDRAM terminates a burst
read after a delay equal to the CAS latency. It will
terminate a burst write and mask data in the current cycle.
3
Rev. 2.4
16Mbit ESDRAM Family
ESDRAM Command Truth Table
CKE
Function
Mode Register Set
Bank Activate
Read
Read with Auto-Precharge
Write
Write with Auto-Precharge
Burst Termination
Single Bank Precharge
Precharge All Banks
Auto-Refresh (CBR)
Self Refresh Entry
Self Refresh Exit
No Operation
Device Deselect
Clock Suspend/Standby
Power Down Mode Entry
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Previous
Cycle
Current
Cycle
/CS
L
L
L
L
L
L
L
L
L
L
L
L
H
X
/RAS
L
L
H
H
H
H
H
L
L
L
L
H
X
X
/CAS
L
H
L
L
L
L
H
H
H
L
L
H
X
X
/WE
L
H
H
H
L
L
L
L
L
H
H
H
X
X
DQM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A11
BS
BS
BS
BS
BS
X
BS
X
X
X
X
X
X
X
X
X
X
X
A10/AP
Op Code
A9-A0
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
L
H
H
X
X
X
X
X
X
X
X
X
H
L
H
X
X
X
L
H
X
X
Row Address
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Column
Column
Column
Column
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP or DESEL
NOP or DESEL
NOP or DESEL
X
X
X
X
X
X
X
X
L
H
Pin Description
Symbol
CLK
CKE
/CS
Type
Input
Input
Input
Function
Clock: All ESDRAM input signals are sampled on the positive edge of CLK.
Clock Enable: Activates the CLK signal when high and deactivates CLK internally. CKE
low initiates the Power Down, Suspend, and Self-Refresh modes.
Chip Select: Active low /CS enables the command decoder and disables the command
decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
Command Inputs: Sampled on the rising edge of CLK, these inputs define the command
to be executed.
Bank Address: This input defines to which of the 2 banks a given command is being
applied. This address input is also used to program the Mode Register.
Address Inputs: A10-A0 defines the row address for the Bank Activate command. A9-A0
define the column address for Read and Write commands. A10/AP invokes the Auto-
Precharge operation. During manual Precharge commands, A10/AP low specifies a
single bank precharge while A10/AP high precharges all banks. The address inputs are
also used to program the Mode Register.
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these
pins and must be set-up and held relative to the rising edge of clock. For Read cycles,
the device drives output data on these pins after the CAS latency is satisfied.
Data I/O Mask Inputs: DQM inputs mask write data (zero latency) and acts as a
synchronous output enable (2 cycle latency) for read data.
Power (+3.3V) and ground for the input buffers and core logic.
Isolated power supply and ground for output buffers. V
DDQ
may be connected to either
3.3V or 2.5V power.
/RAS, /CAS,
/WE
A11 (BS)
A10-A0
Input
Input
Input
DQ15-DQ0
Input/
Output
Input
Supply
Supply
UDQM, LDQM
V
DD
, V
SS
V
DDQ
, V
SSQ
4
Rev. 2.4
16Mbit ESDRAM Family
Mode Register Set (Address Input for Mode Set)
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Operation Mode
CAS Latency
BT
Burst Length
M11
0
0
M10
0
0
M9
0
1
M8
0
0
M7
0
0
Mode
Write
Transfer
No Write
Transfer
M3
0
1
Burst Type
Sequential
Interleaved
Burst Length
M6
0
0
0
0
1
1
1
1
M5
0
0
1
1
0
0
1
1
M4
0
1
0
1
0
1
0
1
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
Sequential
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Interleaved
1
2
4
8
Reserved
Reserved
Reserved
Reserved
5
Rev. 2.4
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
