December, 2012
HI-6130 / HI-6131 / HI-6132
MIL-STD-1553 / MIL-STD-1760
3.3V BC / MT / RT Multi-Terminal Device
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Fully programmable Bus Controller with 28 op
code instruction set.
Simple Monitor Terminal (SMT) Mode records
commands and data separately, with 16-bit or 48-
bit time tagging.
IRIG Monitor Terminal (IMT) Mode supports IRIG-
106 Chapter 10 packet format.
IMT Monitor Mode can optionally generate
complete IRIG-106 data packets, including full
packet headers and trailers.
Independent 16-bit time tag counters and clock
sources for all terminals. The Bus Controller
and Monitor also have 32- and 48-bit time count
options, respectively.
64-Word Interrupt Log Buffer queues the most
recent 32 interrupts. Hardware-assisted interrupt
decoding quickly identifies interrupt sources.
Built-in self-test for protocol logic, digital signal
paths and internal RAM.
Optional self-initialization at reset uses external
serial EEPROM.
±8kV ESD Protection (HBM, all pins).
o
o
Two temperature ranges: -40 C to +85 C, or
o
o
-55 C to +125 C with optional burn-in.
RoHS compliant.
GENERAL DESCPIPTION
The 3.3V CMOS HI-613x device provides a complete
single- or multi-function interface between a host
processor and MIL-STD-1553B bus. Each IC contains
a Bus Controller (BC), a Bus Monitor Terminal (MT)
and two independent Remote Terminals (RTs). Any
combination of the contained 1553 functions can
be enabled for concurrent operation. The enabled
terminals communicate with the MIL-STD-1553 buses
through a shared on-chip dual bus transceiver and
external transformer. The user allocates 64K bytes of
on-chip static RAM between devices to suit application
requirements.
Two options are offered for host access to internal
registers and static RAM: The HI-6130 uses a 16-bit
parallel bus; the HI-6131 communicates with the host
via a 4-wire serial peripheral interface (SPI). The HI-
6132 combines both 16-bit parallel bus and SPI in a
single 15 x 15mm hermetically sealed ceramic package.
Device
HI-6130
HI-6131
HI-6132
Host Interface
16-bit parallel
4-wire SPI
16-bit parallel
or 4-wire SPI
Packages
100-pin PQFP
64-pin QFN
64-pin PQFP
121 ceramic PGA
or LGA
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•
•
•
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Programmable interrupts provide terminal status
to the host processor. Circular data buffers in RAM
have interrupts for rollover and programmable “level
attained”. The HI-613x can be configured for automatic
self-initialization after reset. A dedicated SPI port reads
data from an external serial EEPROM to fully configure
registers and RAM for any subset of one to four terminal
devices.
PIN CONFIGURATION (TOP)
100 - D11
99 - D10
98 - D9
97 - TXINHB
96 - TXINHA
95 - AUTOEN
94 - D8
93 - D7
92 - D6
91 - VCC
90 - GND
89 - D5
88 - D4
87 - D3
86 - RT1SSF
85 - ACTIVE
84 - READY
83 - MTPKRDY
82 - RT2MC8
81 - RT1MC8
80 - ACKIRQ
79 - IRQ
78 - VCC
77 - GND
76 - D2
FEATURES
•
Concurrent multi-terminal operation for one to
four MIL-STD-1553B functions: BC, MT and two
independent RTs.
64K bytes internal static RAM with RAM Error
Detection/Correction option.
Autonomous terminal operation requires minimal
host intervention.
Shared MIL-STD-1553 bus interface reduces
circuit complexity and circuit board area.
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VCC - 1
GND - 2
BCTRIG - 3
D12 - 4
D13 - 5
D14 - 6
D15 - 7
RAMEDC - 8
CE - 9
MODE - 10
STR / OE - 11
VCC - 12
MCLK - 13
GND - 14
WAIT / WAIT - 15
R/W / WE - 16
RT1A_0 - 17
RT1A_1 - 18
RT1A_2 - 19
MR - 20
RT1A_3 - 21
RT1A_4 - 22
A0 - 23
A1 - 24
A2 - 25
HI-6130PQxF
TOP VIEW
75 - D1
74 - D0
73 - WPOL
72 - BTYPE
71 - BENDI
70 - TEST
69 - RT1LOCK
68 - MTSTOFF
67 - BCENA
66 - BUSA
65 - VCCP
64 - BUSA
63 - BUSB
62 - VCCP
61 - BUSB
60 - RT2ENA
59 - RT2A_0
58 - RT2A_1
57 - RT2A_2
56 - RT2A_3
55 - BWID
54 - A15
53 - A14
52 - A12
51 - A13
DS6130 Rev. F
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RT1ENA - 26
A3 - 27
A4 - 28
A5 - 29
RT1AP - 30
MISO - 31
MOSI - 32
A6 - 33
A7 - 34
A8 - 35
VCC - 36
GND - 37
TTCLK - 38
MTTCLK - 39
ECS - 40
EECOPY - 41
ESCK - 42
A9 - 43
A10 - 44
A11 - 45
MTRUN - 46
RT2SSF - 47
RT2LOCK - 48
RT2AP - 49
RT2A_4 - 50
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HI-6130, HI-6131
NOTES:
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HI-6130, HI-6131
Table of Contents
1. BLOCK DIAGRAM ........................................................................................... 14
2. FEATURE OVERVIEW ................................................................................... 15
2.1.
2.2.
2.3.
2.4.
2.5.
Bus Controller Operation .......................................................................................... 15
Remote Terminal Operation ...................................................................................... 15
Monitor Terminal Operation ....................................................................................... 15
Interrupts ................................................................................................................... 15
Reset and Initialization .............................................................................................. 15
3. PIN DESCRIPTIONS ....................................................................................... 16
4. MEMORY MAP................................................................................................. 21
5. RAM STRUCTURES ....................................................................................... 22
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
5.11.
5.12.
5.13.
5.14.
Interrupt Log Data Buffer .......................................................................................... 22
Bus Controller (BC) Instruction List........................................................................... 22
Bus Controller (BC) Msg Control / Status Stack ....................................................... 22
Bus Controller (BC) Call Stack.................................................................................. 22
Bus Controller (BC) General Purpose Queue ........................................................... 22
Monitor Terminal Temporary Buffers A & B ............................................................... 22
Monitor Terminal (MT) Address List .......................................................................... 22
Monitor Terminal (MT) Message Filter Table ............................................................. 22
Monitor Terminal (MT) Data Buffers .......................................................................... 22
RT1 and RT2 Command Illegalization Tables ........................................................... 22
RT1 and RT2 Descriptor Tables ................................................................................ 23
RT1 and RT2 Temporary Receive Buffers ................................................................ 23
RT Message Data Buffers ......................................................................................... 23
RT Storage for Mode Code Commands.................................................................... 23
6. HARDWARE FEATURES ................................................................................ 23
6.1.
6.2.
6.3.
6.4.
6.5.
Remote Terminal Address Inputs .............................................................................. 23
Dual Transceivers for MIL-STD-1553 Bus ................................................................ 23
Encoder and Decoders ............................................................................................. 23
Auto-Initialization Serial EEPROM Interface ............................................................. 23
Selection of Host Interface (HI-6132 only) ................................................................ 24
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HI-6130, HI-6131
7. REGISTER & MEMORY ADDRESSING .......................................................... 24
7.1.
8-bit Bus Operation: (HI-6130 Only) ......................................................................... 24
8. REGISTER DEFINITIONS ............................................................................... 24
9. REGISTERS USED BY ALL DEVICE FUNCTIONS ........................................ 29
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
9.7.
Master Configuration Register (0x0000) ................................................................... 29
Master Status and Reset Register (0x0001) ............................................................ 33
Overview of Interrupts ............................................................................................... 36
Hardware Interrupt Behavior ..................................................................................... 36
Interrupt Count & Log Address Register (0x000A) ................................................... 37
Interrupt Log Buffer ................................................................................................... 38
Hardware Interrupt Registers .................................................................................... 40
9.7.1.
9.7.2.
9.7.3.
Hardware Interrupt Enable Register (0x000F) ...................................................... 40
Hardware Pending Interrupt Register (0x0006) .................................................... 40
Hardware Interrupt Output Enable Register (0x0013) .......................................... 40
9.8.
9.9.
9.10.
Time Tag Counter Configuration ............................................................................... 44
Time Tag Counter Configuration Register (0x0039).................................................. 45
Memory Address Pointer Registers (HI-6131 only)................................................... 49
10.
BUS CONTROLLER − CONFIGURATION AND OPERATION
........................ 51
10.1.
10.2.
10.3.
10.4.
Bus Controller Condition Codes................................................................................ 52
Bus Controller Instruction Op Codes ........................................................................ 55
Bus Controller General Purpose Queue ................................................................... 63
Bus Controller Message Control / Status Blocks ...................................................... 63
10.4.1.
10.4.2.
10.4.3.
10.4.4.
BC Control Word ................................................................................................... 64
Time to Next Message Word ................................................................................. 68
Data Block Pointer ................................................................................................. 68
BC Block Status Word ........................................................................................... 69
11. BUS CONTROLLER REGISTER DESCRIPTION .......................................... 73
11.1.
11.2.
11.3.
11.4.
11.5.
11.6.
BC (Bus Controller) Configuration Register (0x0032) ............................................... 73
Start Address Register for Bus Controller (BC) Instruction List (0x0033) ................. 82
Bus Controller (BC) Instruction List Pointer (0x0034) ............................................... 82
Bus Controller (BC) Frame Time Remaining Register (0x0035) ............................... 83
Bus Controller (BC) Time To Next Message Register (0x0036) ................................ 83
Bus Controller (BC) Condition Code Register (Read 0x0037) .................................. 83
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HI-6130, HI-6131
11.7.
11.8.
11.9.
Bus Controller (BC) General Purpose Flag Register (Write 0x0037) ........................ 86
Bus Controller (BC) General Purpose Queue Pointer Register (0x0038) ................. 86
Bus Controller (BC) Time Tag Counter (0x0043) ...................................................... 87
11.10. Bus Controller (BC) Time Tag Counter High (0x0044) .............................................. 87
11.11. Bus Controller (BC) Time Tag Utility Register (0x0045) ........................................... 88
11.12. Bus Controller (BC) Time Tag Utility High Register (0x0046) .................................. 88
11.13. Bus Controller (BC) Time Tag Match Register (0x0047) .......................................... 88
11.14. Bus Controller (BC) Time Tag Match High Register (0x0048) ................................. 88
11.15. Bus Controller Interrupt Registers and Their Use ..................................................... 89
11.15.1. Bus Controller (BC) Interrupt Enable Register (0x0010) ...................................... 90
11.15.2. Bus Controller (BC) Pending Interrupt Register (0x0007) .................................... 90
11.15.3. Bus Controller (BC) Interrupt Output Enable Register (0x0014) .......................... 90
12. SIMPLE MONITOR TERMINAL (SMT) ............................................................ 93
12.1.
12.2.
12.3.
Overview ................................................................................................................... 93
SMT Block Status Word (BSW) Description ............................................................. 98
SMT Message Filter Table ...................................................................................... 101
13. SIMPLE MONITOR TERMINAL (SMT) REGISTER DESCRIPTION ............. 103
13.1.
13.2.
13.3.
13.4.
13.5.
13.6.
13.7.
13.8.
13.9.
SMT Configuration Register (0x0029) .................................................................... 103
SMT Bus Monitor Address List Start Address Register (0x002F) ........................... 106
SMT Next Message Command Buffer Address (0x0030) ....................................... 106
SMT Last Message Command Buffer Address (0x0031) ........................................ 107
SMT Bus Monitor Time Tag Count Register (0x003A) ............................................ 107
SMT Bus Monitor Time Tag Count Mid Register (0x003B) ..................................... 107
SMT Bus Monitor Time Tag Count High Register (0x003C).................................... 107
SMT Bus Monitor Time Tag Utility Register (0x003D) ............................................. 108
SMT Bus Monitor Time Tag Utility Mid Register (0x003E) ...................................... 108
13.10. SMT Bus Monitor Time Tag Utility High Register (0x003F) ..................................... 108
13.11. SMT Bus Monitor Time Tag Match Register (0x0040) ............................................ 109
13.12. SMT Bus Monitor Time Tag Match Mid Register (0x0041) ..................................... 109
13.13. SMT Bus Monitor Time Tag Match High Register (0x0042) ................................... 109
13.14. SMT Bus Monitor Interrupt Registers and Their Use .............................................. 110
13.14.1. SMT Bus Monitor Interrupt Enable Register (0x0011) ..........................................111
13.14.2. SMT Bus Monitor Pending Interrupt Register (0x0008)........................................111
13.14.3. SMT Bus Monitor Interrupt Output Enable Register (0x0015) ..............................111
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