June, 2012
HI-6120
Parallel Bus Interface and
HI-6121
Serial Peripheral Interface (SPI)
MIL-STD-1553 Remote Terminal ICs
FEATURES
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GENERAL DESCRIPTION
The HI-6120 and HI-6121 provide a complete, integrated,
3.3V MIL-STD-1553 Remote Terminal in a monolithic sili-
con gate CMOS device. Two host interface options are
offered: The HI-6120 uses a 16-bit parallel host bus inter-
face for access to registers and RAM and is offered in a
100-pin plastic quad flat pack (PQFP). The HI-6121 has
a 4-wire SPI (Serial Peripheral Interface) host connection
and comes in a reduced pin count 52-pin PQFP or 9mm
x 9mm 64-pin QFN. Both devices handle all aspects of
the MIL-STD-1553 protocol, including message encod-
ing, decoding, error detection, illegal command detection
and data buffering. Host data management is simplified
by storing message information and data within the on-
chip 32K x 16 static RAM.
A descriptor table in shared RAM provides fully program-
mable memory management. Multiple descriptor tables
can be implemented for fast context switching. Trans-
mit and receive commands can use any of four differ-
ent data buffer modes: indexed (single) buffering, ping-
pong (double) buffering or two circular buffer schemes.
Transmit and receive commands for each subaddress
may use different buffer modes. Mode code commands
employ a simple scheme for storing mode data and mes-
sage information with programmable interrupts.
The device provides internal illegalization capability,
allowing any subset of subaddress, command T/R bit,
broadcast vs non-broadcast and word count (or mode
code) to be illegalized, resulting in a total of 4,096 pos-
sible combinations. The illegalization table resides in in-
ternal RAM. The RT can also operate without illegal com-
mand detection, providing “in form” responses to all valid
commands. Broadcast command recognition is optional.
The HI-6120 and HI-6121 provide programmable inter-
rupts for automatic message handling, message status
and general status. A host interrupt history log maintains
information about the last 16 interrupts.
The HI-6120 and HI-6121 can be configured for automat-
ic self-initialization. A dedicated SPI port reads data from
external serial EEPROM memory to fully configure the
descriptor table, illegalization table and host interrupts.
Internal dual-redundant transceivers provide direct
connection to bus isolation transformers. The device
is offered with industrial temperature range as well as
extended temperature range with optional burn-in. A
“RoHS compliant” lead-free option is also offered.
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Fully integrated 3.3V Remote Terminal meets all
requirements for MIL-STD-1553B Notice 2
Four data buffer modes for subaddress transmit
and receive commands. Data buffer modes are
independently selectable for transmit and receive
commands on each subaddress
Simplified mode code command handling
Integral 16-bit Time-Tag counter has programma-
ble options for clock, interrupts and auto-synchro-
nization
Message information and time-tag words are
stored with message data words for all transacted
messages
In compliance with MIL-STD-1553B Notice 2, re-
ceived data from broadcast messages may be
optionally separated from non-broadcast received
data
Optional interrupt log buffer stores the most recent
16 interrupts to minimize host service duties
Optional illegal command detection uses internal
table
Optional automatic self-initialization at reset
±8kV ESD Protection (HBM, all pins)
MIL-STD-1760 compliant
PIN CONFIGURATION (TOP)
52 - TXINHB
51 - TXINHA
50 - AUTOEN
49 - VCC
48 - GND
47 - SSYSF
46 - ACTIVE
45 - READY
44 - TTCLK
43 - ACKINT
42 - INTMES
41 - INTHW
40 - BENDI
COMP - 1
CE - 2
MODE - 3
SI - 4
SCK - 5
SO - 6
MCLK - 7
RTA0 - 8
RTA1 - 9
RTA2 - 10
MR - 11
RTA3 - 12
RTA4 - 13
HI-6121PQx
HI-6121 in
PQFP-52 Package
39 - TEST
38 - LOCK
37 - MTSTOFF
36 - BUSA
35 - VCCP
34 - BUSA
33 - BUSB
32 - VCCP
31 - BUSB
30 - TEST0
29 - TEST1
28 - TEST2
27 - TEST3
DS6120 Rev. C
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RTAP - 14
MISO - 15
MOSI - 16
VCC - 17
GND - 18
ECS - 19
EECOPY - 20
ESCK - 21
EE1K - 22
TEST7 - 23
TEST6 - 24
TEST5 - 25
TEST4 - 26
06/12
HI-6120, HI-6121
NOTES:
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HI-6120, HI-6121
Table of Contents
1. BLOCK DIAGRAM ........................................................................................... 10
2. PIN DESCRIPTIONS ....................................................................................... 11
3. FUNCTIONAL OVERVIEW .............................................................................. 16
3.1. Shared RAM Utilization .............................................................................................. 16
3.1.1.
3.1.2.
3.1.3.
3.1.4.
3.1.5.
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.2.5.
3.2.6.
Descriptor Table .......................................................................................................... 16
Illegalization Table ....................................................................................................... 16
Message Data Buffers................................................................................................. 16
Storage for Mode Code Commands ........................................................................... 16
Interrupt Log ................................................................................................................ 17
Clock Interrupts ........................................................................................................... 17
Remote Terminal Address Inputs ................................................................................ 17
Integral Time-Tag Counter........................................................................................... 17
Dual Bus Transceivers ................................................................................................ 17
Encoder and Decoders ............................................................................................... 17
Auto-Initialization Serial EEPROM Interface ............................................................... 17
3.2. Hardware Feature Summary ...................................................................................... 17
4. MEMORY AND REGISTER ADDRESSING ..................................................... 18
5. REGISTERS..................................................................................................... 20
5.1. Configuration Register 1 (0x0000)............................................................................ 21
5.2. Configuration Register 2 (0x0001)............................................................................ 24
5.3. Operational Status Register (0x0002) ...................................................................... 28
5.4. Current Command Register (0x0003) ...................................................................... 30
5.5. Current Control Word Address Register (0x0004) .................................................... 30
5.6. Descripter Table Base Address Register (0x0005) .................................................. 30
5.7. Pending Interrupt Register (0x0006) ........................................................................ 31
5.8. 1553 Status Word Bits Register (0x0007) ................................................................ 33
5.9.
Time-Tag Register (0x0008) ..................................................................................... 34
5.10.
Interrupt Log Address Register (0x0009)..................................................................
35
5.11. Current Message Information Word Address Register (0x000A) ............................. 35
5.12. Memory Address Pointer Register (HI-6121 only) (0x000F) ................................... 36
5.13. Interrupt Enable Register (0x0010) .......................................................................... 36
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HI-6120, HI-6121
5.14. Time-Tag Utility Register (0x0011)............................................................................ 38
5.15. Bus A Select Register (0x0012) ................................................................................
39
5.16. Bus B Select Register (0x0013) ...............................................................................
39
5.17. Built-in Test Word Register (0x0014) ........................................................................ 40
5.18. Alternate Built-in Test Word Register (0x0015) ........................................................ 41
5.19.
Reserved Register (0x0016)..................................................................................... 41
5.20. Test Control Register (0x0017) ................................................................................ 41
5.21. Loopback Test Transmit Data Register (0x0018) ..................................................... 45
5.22.
Loopback Test Receive Data Register (0x0019)
...................................................... 45
6. COMMAND RESPONSES ............................................................................... 46
6.1. RT to RT Commands. ................................................................................................ 47
7. COMMAND ILLEGALIZATION TABLE ............................................................. 48
8. TEMPORARY RECEIVE DATA BUFFER......................................................... 52
9.
INTERRUPT LOG BUFFER ............................................................................. 52
10. DESCRIPTOR TABLE ...................................................................................... 55
10.1. Receive Subaddress Control Word ............................................................................ 57
10.2. Transmit Subaddress Control Word ........................................................................... 60
10.3. Data Buffer Options for Mode Code Commands ........................................................ 62
10.4. Receive Mode Command Control Word ..................................................................... 63
10.5. Transmit Mode Command Control Word .................................................................... 65
11. MESSAGE DATA BUFFERS ............................................................................
69
11.1. Subaddress Message Information Words ................................................................. 70
11.1.1. Receive Subaddress Command ................................................................................ 70
11.1.2. Transmit Subaddress Command ............................................................................... 72
11.2. Mode Command Message Information Words ........................................................... 73
11.2.1. Receive Mode Command ........................................................................................... 73
11.2.2. Transmit Mode Command .......................................................................................... 75
11.3. Ping-Pong Data Buffering ........................................................................................... 78
11.3.1. Double Buffered (Ping-Pong) Mode ............................................................................ 78
11.3.2. Ping-Pong Enable / Disable Handshake ..................................................................... 78
11.3.3. Broadcast Message Handling in Ping-Pong Mode ..................................................... 80
11.4. Indexed Data Buffer Mode.......................................................................................... 82
11.4.1. Single Message Mode................................................................................................. 82
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HI-6120, HI-6121
11.4.2. Broadcast Message Handling in Index Mode ............................................................. 82
11.5. Circular Buffer Mode 1................................................................................................ 86
11.6. Circular Buffer Mode 2................................................................................................
90
12. MODE COMMAND PROCESSING..................................................................
95
12.1. General Considerations ..............................................................................................
95
12.2. Mode Command Interrupts .........................................................................................
95
12.3. Mode Command Data Words .....................................................................................
95
12.4. Standard Mode Command Processing.......................................................................
98
12.5. Simplified Mode Command Processing......................................................................
98
13. INTERRUPT MANAGEMENT ..........................................................................
99
13.1. Host Message Detection Options ...............................................................................
99
13.2. Host Interrupt Generation ...........................................................................................
99
13.2.1. Interrupt Log Address Register ................................................................................. 100
13.2.2. Interrupt Address Word (IAW) ................................................................................... 100
13.2.3. Interrupt Identification Word (IIW) ............................................................................ 100
14. RESET AND INITIALIZATION ........................................................................ 101
14.1. Master Reset using the MR pin and Optional Auto-Initialization............................... 101
14.2. Software Reset ......................................................................................................... 105
14.3. Reset Remote Terminal Mode Code ........................................................................ 105
14.4. Serial EEPROM Programming Utility ...................................................................... 105
15. HOST INTERFACE ........................................................................................ 107
15.1. HI-6120 Host Bus Interface ...................................................................................... 107
15.1.1. Bus Wait States and Data Prefetch........................................................................... 107
15.2. HI-6121 Serial Peripheral Interface .......................................................................... 108
15.2.1. Serial Peripheral Interface (SPI) Basics ................................................................... 108
15.2.2. HI-6121 SPI Commands ...........................................................................................
109
15.2.3. Fast-Access Commands for Registers 0-15 ............................................................
109
15.2.4. Indirect Addressing of RAM and Registers ..............................................................
109
15.2.5. Data Prefetch for SPI Read Cycles ............................................................................111
15.2.6. Special Purpose Commands......................................................................................111
15.2.7. Descriptor Table Prefetch Exceptions ....................................................................... 113
16. APPENDIX: RT MESSAGES RESPONSES, OPTIONS & EXCEPTIONS ... 117
17. ELECTRICAL CHARACTERISTICS .............................................................. 144
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