TS80C51U2
TS83C51U2
TS87C51U2
Double UART 8-bit CMOS Microcontroller, 0-60 MHz
1. Description
TEMIC TS80C51U2 is high performance CMOS ROM,
OTP and EPROM versions of the 80C51 CMOS single
chip 8-bit microcontroller.
The TS80C51U2 retains all features of the TEMIC
80C51 with extended ROM/EPROM capacity (16
Kbytes), 256 bytes of internal RAM, a 7-source , 4-level
interrupt system, an on-chip oscilator and three timer/
counters.
In addition, the TS80C51U2 has a second UART,
enhanced functions on both UART, enhanced timer 2,
a hardware watchdog timer, a dual data pointer, a baud
rate generator and a X2 speed improvement mechanism.
The fully static design of the TS80C51U2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C51U2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q
80C52 Compatible
•
8051 pin and instruction compatible
•
Four 8-bit I/O ports
•
Three 16-bit timer/counters
•
256 bytes scratchpad RAM
q
q
Asynchronous port reset
Interrupt Structure with
•
7 Interrupt sources
•
4 level priority interrupt system
q
Full duplex Enhanced UARTs
•
Framing error detection
•
Automatic address recognition
q
High-Speed Architecture
•
40 MHz @ 5V, 30MHz @ 3V
•
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q
q
Low EMI (inhibit ALE)
Power Control modes
•
Idle mode
•
Power-down mode
•
Power-off Flag
q
q
q
q
q
second UART
Baud Rate Generator
Dual Data Pointer
On-chip ROM/EPROM (16K-bytes)
Programmable Clock Out and Up/Down Timer/
Counter 2
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
q
q
q
Once mode (On-chip Emulation)
Power supply: 4.5-5.5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85
o
C)
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44
(window), CDIL40 (window)
q
q
3. The second UART
In this document, UART_0 will make reference to the
first UART (present in all TEMIC Semiconductors C51
derivatives) and UART_1 will make reference to the
second UART, only present in the TS80C51U2 part.
The second UART (UART_1) can be seen as an alternate
function of Port 1 (P1.2 or P1.6 for RXD1 and P1.3 or
P1.7 for TXD1) or can be connected to (pin6 or pin12)
Rev. C - Aug. 24, 1999
1
TS80C51U2
TS83C51U2
TS87C51U2
and (pin28 or pin34) of 44-pin package (see Pin configuration). UART_1 is fully compliant with the first one
allowing an internal baud rate generator to be the clock source. This common internal baud rate generator can be
used independently by each UART or both as clock source allowing to program various speeds.
The TS80C51U2 provides 7 sources of interrupt with four priority levels. UART_1 has a lower priority than Timer
2. The Serial Ports are full duplex meaning they can transmit and receive simultaneously. They are also receive
buffered, meaning they can start reception of a second byte before a previously received byte has been read from
the receive register. The Serial Port receive and transmit registers of UART_1 are both accessed at Special Function
Register SBUF_1. Writing to SBUF_1 loads the transmit register and reading SBUF_1 accesses a physical separate
receive register.
The UART_1 port control and status is the Special Function Register SCON_1. This register contains not only the
mode selection bit but also the 9th bit for transmit and receive (TB8_1 and RB8_1) and the serial port interrupt
bits (TI_1 and RI_1). The automatic address recognition feature is enabled when multiprocessor communication
is enabled. Implemented in hardware, automatic address recognition enhances the multiprocessor communication
feature by allowing the Serial Port to examine address of each incoming frame and provides filtering capability.
The UART_1 also comes with Frame error detection, similar to the UART_0.
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Rev. C - Aug. 24, 1999
TS80C51U2
TS83C51U2
TS87C51U2
5. SFR Mapping
The Special Function Registers (SFRs) of the TS80C51U2 fall into the following categories:
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
•
I/O port registers: P0, P1, P2, P3
•
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
•
Serial I/O port registers for UART_0: SADDR_0, SADEN_0, SBUF_0, SCON_0
•
Serial I/O port registers for UART_1: SADDR_1, SADEN_1, SBUF_1, SCON_1
•
Baud Rate Generator registers: BRL, BDRCON, BDRCON_1
•
Power and clock control registers: PCON
•
HDW Watchdog Timer Reset: WDTRST, WDTPRG
•
Interrupt system registers: IE, IP, IPH
•
Others: AUXR, CKCON
Table 2. All SFRs with their address and their reset value
Bit
address-
able
0/8
1/9
2/A
3/B
Non Bit addressable
4/C
5/D
6/E
7/F
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
PSW
0000 0000
T2CON
0000 0000
SCON_1
0000 0000
IP
X000 0000
P3
1111 1111
IE
0X00 0000
P2
1111 1111
SCON_0
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8
TMOD
0000 0000
SP
0000 0111
1/9
TL0
0000 0000
DPL
0000 0000
2/A
TL1
0000 0000
DPH
0000 0000
3/B
4/C
5/D
6/E
TH0
0000 0000
TH1
0000 0000
AUXR
00XX XXX0
CKCON
XXXX XXX0
PCON
00X1 0000
7/F
SBUF_0
XXXX XXXX
SADDR_0
0000 0000
SADDR_1
0000 0000
AUXR1
XXXX XXX0
BRL
0000 0000
BDRCON
0XXX 0000
BDRCON_1
0X00 00XX
WDTRST
XXXX XXXX
WDTPRG
XXXX X000
T2MOD
XXXX XX00
SBUF_1
XXXX XXXX
SADEN_0
0000 0000
SADEN_1
0000 0000
IPH
X000 0000
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
ACC
0000 0000
B
0000 0000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
reserved
4
Rev. C - Aug. 24, 1999
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