Schmitt Octal Bus Transceiver with Three-State Outputs
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Three-state outputs drive bus line directly
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
UT54ACS245S - SMD 5962-96572
DESCRIPTION
The UT54ACS245S is a non-inverting octal bus transceiver with
Schmitt Trigger input levels. The circuit is designed for asyn-
chronous two-way communication between data buses. The
control function implementation minimizes external timing re-
quirements.
The device allows data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic level
at the direction control (DIR) input. The enable input (G) dis-
ables the device so that the buses are effectively isolated.
The device is characterized over full military temperature range
of -55°C to +125°C.
FUNCTION TABLE
ENABLE
G
L
L
H
DIRECTION
CONTROL DIR
L
H
X
OPERATION
B Data To A Bus
A Data To B Bus
Isolation
PINOUTS
20-Pin DIP
Top View
DIR
A1
A2
A3
A4
A5
A6
A7
A8
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
G
B1
B2
B3
B4
B5
B6
B7
B8
20-Lead Flatpack
Top View
DIR
A1
A2
A3
A4
A5
A6
A7
A8
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
G
B1
B2
B3
B4
B5
B6
B7
B8
LOGIC SYMBOL
G
DIR
(19)
(1)
G3
3 EN1 (BA)
3 EN2 (AB)
(18)
1
2
(17)
(16)
(15)
(14)
B1
B2
B3
B4
A1
A2
A3
A4
A5
A6
A7
A8
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
B5
(13)
B6
(12)
B7
(11)
B8
1
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
LOGIC DIAGRAM
DIR
(1)
(19)
G
A1
(2)
(18)
B1
A2
(3)
(17)
B2
A3
(4)
(16)
B3
A4
(5)
(15)
B4
A5
(6)
(14)
B5
A6
(7)
(13)
B6
A7
(8)
(12)
B7
A8
(9)
(11)
B8
2
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
3
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
3
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
V
T
+
V
T
-
V
H
PARAMETER
Schmitt Trigger, positive going threshold
1
ACS
Schmitt Trigger, negative going threshold
1
ACS
Schmitt Trigger, typical range of hysteresis
2
CONDITION
MIN
MAX
.7V
DD
UNIT
V
V
.3V
DD
ACS
I
IN
V
OL
V
OH
I
OL
Input leakage current
ACS
Low-level output voltage
3
ACS
High-level output voltage
3
ACS
Output current (Sink)
10
V
IN
= V
DD
or V
SS
I
OL
= 100μA
I
OH
= -100μA
V
IN
=V
DD
or V
SS
V
OL
=0.4V
I
OH
Output current (Source)
10
V
IN
=V
DD
or V
SS
V
OH
=V
DD
- 0.4
I
OZ
I
OS
P
total
I
DDQ
C
IN
C
OUT
Three-state output leakage current
Short-circuit output current
2, 4
ACS
Power dissipation
2, 8, 9
Quiescent Supply Current
Input capacitance
5
Output capacitance
5
V
O
= V
DD
and V
SS
V
O
= V
DD
and V
SS
C
L
= 50pF
V
DD
= 5.5V
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
0.6
-1
1.5
1
V
μA
0.25
V
V
DD
- 0.25
12
V
mA
-12
mA
-30
30
μA
-300
300
2.0
10
15
15
mA
mW/
MHz
μA
pF
pF
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit, but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4.Not more than one output may be shorted at a time for maximum duration of one second.
5.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10.Guaranteed based on characterization data, but not tested.
1 Introduction
In the mid-1960s, American scientist Maas conducted extensive experimental research on the charging process of open-cell batteries and proposed an acceptable charging curve for ...[详细]
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