THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
MA8255
APRIL 1995
DS3815-1.4
MA8255
RADIATION HARD PROGRAMMABLE PERIPHERAL INTERFACE
The MA8255 is a general purpose programmable Input/
Output device designed for use with the MA31750
microprocessor. It has 24 I/O pins which may be individually
programmed in 2 groups of 12 and used in 3 major modes of
operation.
In the first mode (MODE 0), each group of 12 I/O pins may
be programmed in sets of 4 to be inputs or outputs. In the
second mode (MODE 1), each group may be programmed to
have 8 lines of input or output. Of the remaining 4 pins, 3 are
used for hand-shaking and interrupt control signals. The third
mode of operation (MODE 2) is the bidirectional bus mode,
which uses 8 lines for a bidirectional bus and 5 lines, borrowing
one from the other group, for hand-shaking.
FEATURES
s
Radiation Hard to 1MRad (Si)
s
High SEU Immunity, Latch Up Free
s
Silicon-on-Sapphire Technology
s
24 Programmable l/O Pins
s
All Inputs and Outputs are TTL Compatible
s
Direct Bit Set/Reset Capability Easing Control Application
Interface
s
Replaces Several MSI Packages
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Compatible with MA31750 (Mil-Std-1750A)
Microprocessor
RDN
WRN
CSN
Figure 1: Block Diagram
1
MA8255
FUNCTIONAL DESCRIPTION
The MA8255 is a programmable peripheral interface (PPI)
device designed for use with MA31750. Its function is that of a
general purpose l/O component to interface peripheral
equipment to the microcomputer system bus. The functional
configuration of the MA8255 is programmed by the system
software so that, normally, no external logic is necessary to
interface peripheral devices or structures.
Data Bus Buffer
This 3-state, bidirectional, 8-bit buffer is used to interface
the MA8255 to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status information
are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal
and external transfers of both Data and Control Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
Reset (RESET)
A high on this input clears the control register and all ports
(A,B,C) are set to the input mode.
Chip Select (CSN)
A low on this input pin enables the communication between
the MA8255 and the CPU.
Read Select (RDN)
A low pulse on RDN indicates a CPU read from the
MA8255.
Write Select (WRN)
A low pulse on WRN indicates a write from the CPU to the
MA8255.
Port Select O and Port Select 1 (AO and A1 )
These input signals, in conjunction with the RDN and WRN
inputs, control the selection of one of the three ports of the
control word registers. They are normally connected to the
least significant bits of the address bus.
Basic Operation
A1 A0 RDN WRN CSN
0
0
1
0
0
1
1
x
1
x
0
1
0
0
1
0
1
x
1
x
0
0
0
1
1
1
1
x
0
1
1
1
1
0
0
0
0
x
1
1
0
0
0
0
0
0
0
1
0
0
READ
PORT A
→
DATA BUS
PORT B
→
DATA BUS
PORT C
→
DATA BUS
WRITE
DATA BUS
→
PORT A
DATA BUS
→
PORT B
DATA BUS
→
PORT C
DATA BUS
→
CONTROL
DISABLE
DATA BUS
→
TRI-STATE
ILLEGAL CONDITION
DATA BUS
→
TRI-STATE
Table 1: Basic Operation
OPERATIONAL DESCRIPTION
Mode Selection
There are three basic modes of operation, which can be
selected by the system software:
Mode 0. Basic Input/Output
Mode 1. Strobed Input/Output
Mode 2 Bi-directional Bus
When the reset input goes high all ports will be set to the
input mode (i.e. all 24 lines will be in the high impedance state)
After the reset is removed the MA8255 can remain in the input
mode with no additional initialisation required.
During the execution of the system program any of the
other modes may be selected using a single output instruction.
This allows a single MA8255 to service a variety of peripheral
devices with a single software maintenance routine.
The modes for Port A and Port B can be separately
defined, while Port C is divided into two portions as required by
the Port A and Port B definitions. All of the output registers,
including the status register, will be reset whenever the mode
is changed.
Modes may be combined so that their functional definition
can be tailored to almost any l/O structure. For instance; Group
B can be programmed in Mode 0 whilst simultaneously Group
A could be programmed in Mode 1.
2
MA8255
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a
single output instruction. This feature reduces software
requirements in control-based applications.
When Port C is being used as Status/Control for Port A or
B, these bits can be set or reset by using the Bit Set/Reset
operation just as if they were data output ports.
Interrupt Control Functions
A
WRN, RDN
A
0
-A
1
, CSN
MA8255
C
A
A
When the MA8255 is programmed to operate in Mode 1 or
2, control signals are provided that can be used as interrupt
request inputs to the CPU (figure 4). The interrupt request
signals, generated from Port C, can be inhibited or enabled by
setting or resetting the associated INTE register bit, using the
Bit Set/Reset function of Port C.
This function allows the programmer to disallow or allow a
specific l/O device to interrupt the CPU, without affecting any
other device in the interrupt structure.
INTE register bit definitions:
(BIT-SET): INTE is SET -Interrupt enable
(BIT-RESET): INTE is RESET -Interrupt disable
Note: All mask register bits are automatically reset during
mode selection and device reset.
Figure 2: Basic Mode Definitions and Bus Interface
Mode Definition Format (D
7
= 1)
Bit Set/Reset Format (D
7
= 0)
BIT No.
S
E
L
B
0
B
1
B
2
Figure 4: Bit Set/Reset Format (D
7
= 0)
Figure 3: Mode Definition Format (D
7
= 1)
3
MA8255
Group A and Group B Controls
The functional configuration of each port is programmed by
the system software. In essence, the CPU outputs a control
word to the MA8255. The control word contains information
such as mode, bit set, bit reset, etc., this initializes the
functional configuration of the MA8255.
Each of the Control blocks (Group A and Group B) accept
commands from the Read/Write Control Logic, receive control
words from the internal data bus and issue the proper
commands to its associated ports:
Control Group A - Port A and Port C upper (C7-C4) Control
Group B - Port B and Port C lower (C3-C0)
The Control Word Register can only be written into.
Therefore reading of the Control Word Register is not allowed.
Ports A, B and C
The MA8255 contains three 8-bit ports (A, B, and C). All
can be configured in a wide variety of functional characteristics
by the system software but each has its own special features
to further enhance the power and flexibility of the MA8255.
Port A.
One 8-bit data output latch/buffer and one 8-bit data input
latch.
Port B.
One 8-bit data input/output latch/buffer and one 8-bit input
buffer
Port C.
One 8-bit data output latch/buffer and one 8-bit data input
buffer (no latch for input). This port can be divided into two 4-bit
ports under the mode control. Each 4-bit port contains a 4-bit
latch and it can be used for the control signal outputs and
status signal inputs in conjunction with ports A and B
OPERATING MODE 0
(Basic Input/Output)
This functional configuration provides simple input and
output operation for each of the three ports. No handshaking is
required; data is simply written to or read from a specified port.
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Two 8-bit ports and 4-bit ports
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Any port can be input or output
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Outputs are latched
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Inputs are not latched.
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16 different Input/Output configurations are possible in this
Mode.
RDN
WRN
INPUT PORT
CSN, A1, A0
Figure 5: Basic Input (Read) Timing Diagram
4
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