Low Power CMOS SRAM
256K X 8 Bits
Features:
• Vcc operation voltage : 1.5V ~ 3.6V
• Low power consumption :
15mA (Max.) operating current
1uA (Typ.) CMOS standby current
• High Speed Access time :
70ns (Max.) at Vcc = 1.5V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Data retention supply voltage as low as 1.2V
• Easy expansion with CE\ and OE\ options
UC62LV2008
-55/-70
Description
The UC62LV2008 is a high performance, very low power
CMOS Static Random Access Memory organized as 262,144
words by 8 bits and operates from 1.5V to 3.6V supply
voltage. Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a
typical CMOS standby current of 1uA and maximum access
time of 70ns in 1.5V operation.
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LV2008 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The UC62LV2008 is available in the JEDEC standard 32 pin
450mil Plastic SOP, 8mmx20.0mm TSOP (type I), and
8mmx13.4mm STSOP.
PRODUCT FAMILY
Product Family
UC62LV2008HC
UC62LV2008FC
UC62LV2008GC
UC62LV2008AC
UC62LV2008HI
UC62LV2008FI
UC62LV2008GI
UC62LV2008AI
Operating
Tempature
Vcc Range
Speed
(ns)
Vcc=1.5V(Max.)
Power Consumption
STANDBY
Operating
Vcc=3.3V(Typ.)
1uA
Vcc=3.6V(Max.)
15mA
Package
Type
TSOP-32
SOP-32
STSOP-32
DICE
TSOP-32
SOP-32
STSOP-32
DICE
0℃ ~ 70℃
1.5V ~ 3.6V
55/70
-40℃ ~ 85℃
1.5V ~ 3.6V
55/70
1uA
15mA
PIN CONFIGURATIONS
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
32
1
31
2
30
3
29
4
28
5
27
6
26
7
25
8
9 UC62LV2008FI 24
10 UC62LV2008FC 23
22
11
21
12
20
13
19
14
15
18
16
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
BLOCK DIAGRAM
ROW
DECODER
ROW
Address
ADDRESS INPUT
BUFFER
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
UC62LV2008HI
UC62LV2008GI
UC62LV2008HC
UC62LV2008GC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
CE2
CE
WE
OE
A0 - A17
MEMORY ARRAY
256K X 8 Bits
COL
Address
COLUMN DECODER
CE
WE
OE
SENSE AMPLIFIER
&
WRITE DRIVER
CONTROL
INPUT
BUFFER
CONTROL
BLOCK
X8
I/O BUFFER
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev.1.0
PAGE
1
Low Power CMOS SRAM
256K X 8 Bits
PIN DESCRIPTION
Name
A0 – A17
CE\,CE2
Type
Input
Input
Function
UC62LV2008
-55/-70
Address inputs for selecting one of the 262,144 x 8 bit words in the RAM
CE\ is active LOW. CE2 is active HIGH.Chip enable must be active when data read from or write
to the device. If chip enable is not active, the device is deselected and not in a standby power
down mode. The DQ pins will be in high impedance state when the device is deselected.
WE\
Input
The Write enable input is active LOW and controls read and write operations. With the chip
selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when
WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.
OE\
Input
The output enable input is active LOW. If the output enable is active while the chip is selected
and the write enable is inactive, data will be present on the DQ pins and they will be enabled.
The DQ pins will be in the high impedance state when OE\ is inactive.
DQ0 – DQ7
Vcc
Gnd
I/O
Power
Power
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
Mode
Not Selected
Not Selected
Output Disabled
Read
Write
WE\
X
X
H
H
L
CE\
H
X
L
L
L
CE2
X
L
H
H
H
OE\
X
X
H
L
X
I/O state
High Z
High Z
High Z
D
OUT
D
IN
Vcc Current
I
SB
,I
SB1
I
SB
,I
SB1
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
PT
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5 to V
CC
+0.5
-40 to 125
-50 to 150
0.5
10
UNIT
V
℃
℃
W
mA
OPERATING RANGE
RANGE
Commercial
AMBIENT
TEMPERATURE
0℃ to 70℃
V
CC
1.5V ~ 3.6V
CAPACITANCE
(1)
(TA=25℃,f=1.0MHz)
SYMBOL
CIN
PARAMETER
CONDITIONS MAX.
UNIT
Input
VIN=0V
6
pF
Capacitance
Input/Output
VDQ
8
pF
CDQ
Capacitance
1. This parameter is guaranteed and not 100% tested.
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev.1.0
PAGE
2
Low Power CMOS SRAM
256K X 8 Bits
DC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃)
Symbol
V
IL
V
IH
I
L
I
OL
V
OL
V
OH
I
CC
I
SB1
I
SB2
UC62LV2008
-55/-70
Comment
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
TTL Standby Current
CMOS Standby Current
Test Condition
V
CC
=2.4V
V
CC
=3.6V
V
CC
=MAX V
IN
=0V to V
CC
V
CC
=MAX CE\=V
IH
or OE\=V
IH
V
IO
=0V t V
CC
V
CC
=3.6V, I
OL
=2mA
V
CC
=3.0V, I
OH
=1mA
CE\=V
IL
,I
DQ
=0mA, F=Fmax
CE\=V
IH
, V
IN
=V
IH
to V
IL
CE\≧V
CC
-0.2V, V
IN
=V
CC
-0.2V
to 0.2V
(3)
MIN.
-0.5
2.0
-
-
-
2.4
-
-
-
TYP.
(1)
-
-
-
-
-
-
-
-
1
MAX.
0.8
Vcc-0.2
1
1
0.4
-
15
1
5
UNITS
V
V
uA
uA
V
V
mA
mA
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA=0℃ to 70℃)
Symbol
V
DR
I
CCDR
t
DR
t
R
1.
2.
Comment
VCC to Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Test Condition
CE\≧V
CC
- 0.2V
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE\≧V
CC
- 0.2V
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
See Retention Waveform
T
RC
(2)
MIN.
1.2
-
0
TYP.
-
(1)
MAX.
-
0.5
-
-
UNITS
V
uA
ns
ns
0.05
-
-
V
CC
= 1.5V, TA = 25℃.
t
RC
= Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM
(1)
(CE\ Controlled)
Vcc
CE
t
CDR
VIH
Data Retention Mode
V
DR
>= 1.2V
CE >= V
CC
- 0.2V
t
R
VIH
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev.1.0
PAGE
3
Low Power CMOS SRAM
256K X 8 Bits
UC62LV2008
-55/-70
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
VCC/0V
1V/ns
0.5VCC
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
MUST BE
STEADY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE
STATE
UNKNOWN
AC TEST LOADS AND WAVEFORMS
3.3V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
3.3V
MAY CHANGE
FROM H TO L
1269Ω
1269Ω
OUTPUT
OUTPUT
MAY CHANGE
FROM L TO H
DON’T CARE
ANY CHANGE
PERMITTED
1404Ω
FIGURE 1A
FIGURE 1B
DOES NOT
APPLY
1404Ω
100pF
5pF
TERMINAL EQUIVALENT
667Ω
OUTPUT
1.73V
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
ALL INPUT PULSES
V
CC
90%
10%
90%
10%
GND
FIGURE 2
1V/ns
1V/ns
AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, V
CC
=1.5V~3.6V)
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
CE
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Address Chang to Output Change
UC62LV2008-55
Min
55
-
-
-
10
5
-
-
10
Typ
-
-
-
-
-
-
-
-
-
Max
-
55
55
30
-
-
20
20
-
UC62LV2008-70
Min
70
-
-
-
10
5
-
-
10
Typ
-
-
-
-
-
-
-
-
-
Max
-
70
70
35
-
-
20
20
-
UNIT
Ns
Ns
Ns
Ns
Ns
Ns
Ns
Ns
Ns
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev.1.0
PAGE
4
Low Power CMOS SRAM
256K X 8 Bits
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
UC62LV2008
-55/-70
t
OH
READ CYCLE2
(1,3,4)
CE
t
CLZ (5)
D
OUT
t
CE
t
CHZ (5)
READ CYCLE3
(1,4)
t
RC
ADDRESS
t
AA
OE
t
OE
CE
t
OLZ
t
CLZ (5)
D
OUT
NOTES:
1. WE\ is high in read cycle.
2. Device is continuously selected when CE\ = VIL
3. Address valid prior to or coincident with CE\ transition low.
4. OE\ = VIL.
5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
t
OH
t
OHZ (1,5)
t
CE
t
CHZ (5)
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev.1.0
PAGE
5
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