Low Power CMOS SRAM
256K X 16
Features:
• Vcc operation voltage : 1.5 V~ 3.6V
• Low power consumption :
35mA (Max.) operating current
2uA (Typ.) CMOS standby current
• High Speed Access time :
70ns (Max.) at Vcc = 1.5V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Data retention supply voltage as low as 1.2V
• Easy expansion with CE\ and OE\ options
UC62LV4096
-55/-70
Description
The UC62LV4096 is a high performance, low power
CMOS Static Random Access Memory organized as 262,144
words by 16 and operates from 1.5 V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide
both high speed and low power features with a typical CMOS
standby current of 2uA and maximum access time of 70ns in
1.5V operation.
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LV4096 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The US62LV4096 is available in the JEDEC standard 44
pin TSOP (Type II) and 48 pin mini-BGA.
PRODUCT FAMILY
Product Family
UC62LV4096JC
UC62LV4096KC
UC62LV4096AC
UC62LV4096JI
UC62LV4096KI
UC62LV4096AI
Operating
Tempature
0
℃
~ 70
℃
Vcc Range
Speed
(ns)
Vcc=1.5V(Max.)
Power Consumption
STANDBY
Operating
Vcc=3.3V(Typ.)
2uA
Vcc=3.6V(Max.)
35mA
Package
Type
TSOP-44
BGA-48
DICE
TSOP-44
BGA-48
DICE
1.5V ~ 3.6V
55/70
-40
℃
~ 85℃
1.5V ~ 3.6V
55/70
2uA
35mA
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A17
BLOCK DIAGRAM
ROW
DECODER
ROW
Address
ADDRESS INPUT
BUFFER
A0 - A17
MEMORY ARRAY
256K X 16 Bits
UC62LV4096JC
UC62LV4096JI
COL
Address
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
X16
I/O BUFFER
CE
WE
OE
UB
LB
CONTROL INPUT
BUFFER
CONTROL
BLOCK
CE
WE
OE
UB
LB
LB
OE
A0
A1
A2
NC
DQ0 ~ DQ15
DQ8
UB
A3
A4
CE
DQ0
DQ9
DQ10
A5
A6
DQ1
DQ2
GND
DQ11
NC
A7
DQ3
VCC
VCC
DQ12
NC
A16
DQ4
GND
DQ14
DQ13
A14
A15
DQ5
DQ6
DQ15
NC
A12
A13
WE
DQ7
NC
A8
A9
A10
A11
A17
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0
PAGE
1
Low Power CMOS SRAM
256K X 16
PIN DESCRIPTION
Name
A0 – A17
CE\
Type
Input
Input
Function
UC62LV4096
-55/-70
Address inputs for selecting one of the 262,144 x 16 bit words in the RAM
CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip
enable is not active, the device is deselected and not in a standby power down mode. The DQ
pins will be in high impedance state when the device is deselected.
WE\
Input
The Write enable input is active LOW and controls read and write operations. With the chip
selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when
WE\ is LOW, the data present on the DQ pins will be written into the selected memory location.
OE\
Input
The output enable input is active LOW. If the output enable is active while the chip is selected
and the write enable is inactive, data will be present on the DQ pins and they will be enabled.
The DQ pins will be in the high impedance state when OE\ is inactive.
UB\ and LB\
DQ0 – DQ15
Vcc
Gnd
Input
I/O
Power
Power
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
Mode
Not Selected
Output Disabled
WE\
X
H
X
H
CE\
H
L
L
L
L
L
L
L
L
OE\
X
H
X
L
L
L
X
X
X
LB\
X
X
H
L
H
L
L
H
L
UB\
X
X
H
H
L
L
H
L
L
I/O 0 ~ 7
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
High Z
D
IN
I/O 8 ~ 15
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
Vcc Current
I
SB
,I
SB1
I
CC
Read
H
H
L
I
CC
Write
L
L
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
PT
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5 to V
CC
+0.5
-40 to 125
-50 to 150
0.5
10
UNIT
V
℃
℃
W
mA
OPERATING RANGE
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0℃ to 70℃
-40℃ to 85℃
V
CC
1.5V ~ 3.6V
1.5V ~ 3.6V
CAPACITANCE
(1)
(TA=25℃,f=1.0MHz)
SYMBOL
CIN
PARAMETER
CONDITIONS MAX.
UNIT
Input
VIN=0V
6
pF
Capacitance
Input/Output
VDQ
8
pF
CDQ
Capacitance
1. This parameter is guaranteed and not 100% tested.
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0
PAGE
2
Low Power CMOS SRAM
256K X 16
DC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃)
Symbol
V
IL
V
IH
I
L
I
OL
V
OL
V
OH
I
CC
I
SB1
I
SB2
UC62LV4096
-55/-70
Comment
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
TTL Standby Current
CMOS Standby Current
o
Test Condition
V
CC
=2.4V
V
CC
=3.6V
V
CC
=3.6V V
IN
=0V to V
CC
V
CC
=3.6V CE\=V
IH
or OE\=V
IH
V
IO
=0V t V
CC
V
CC
=3.6V, I
OL
=2mA
V
CC
=3.0V, I
OH
=-1mA
CE\=V
IL
,I
DQ
=0mA, F=Fmax
CE\=V
IH
, V
IN
=V
IH
to V
IL
CE\≧V
CC
-0.2V, V
IN
=V
CC
-0.2V
(4)
or 0.2V , F=0
(3)
MIN.
-0.5
2.0
-
-
-
2.4
-
-
-
TYP.
(1)
-
-
-
-
-
-
-
-
2
MAX.
0.8
Vcc-0.2
1
1
0.4
-
35
1
10
UNITS
V
V
uA
uA
V
V
mA
mA
uA
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC .
4. F=0 means input signals must be keep in static state.
DATA RETENTION CHARACTERISTICS ( TA=0℃ to 70℃)
Symbol
V
DR
I
CCDR
t
DR
t
R
1.
2.
Comment
VCC to Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Test Condition
CE\≧V
CC
- 0.2V
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE\≧V
CC
- 0.2V
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
See Retention Waveform
T
RC
(2)
MIN.
1.2
-
0
TYP.
-
(1)
MAX.
-
1
-
-
UNITS
V
uA
ns
ns
0.1
-
-
V
CC
= 1.5V, TA = 25℃.
t
RC
= Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM
(1)
(CE\ Controlled)
Vcc
CE
t
CDR
VIH
Data Retention Mode
V
DR
>= 1. 2V
CE >= V
CC
- 0. 2V
t
R
VIH
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0
PAGE
3
Low Power CMOS SRAM
256K X 16
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
VCC to 0V
1V/ns
0.5V
CC
UC62LV4096
-55/-70
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
1269Ω
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE
STATE
UNKNOWN
AC TEST LOADS AND WAVEFORMS
3.3V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
3.3V
1269Ω
OUTPUT
OUTPUT
MAY CHANGE
FROM L TO H
DON’T CARE
ANY CHANGE
PERMITTED
1404Ω
100pF
FIGURE 1A
FIGURE 1B
DOES NOT
APPLY
1404Ω
5pF
TERMINAL EQUIVALENT
667Ω
OUTPUT
1.73V
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
ALL INPUT PULSES
V
CC
GND
10%
90%
90%
10%
FIGURE 2
1V/ns
1V/ns
AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, V
CC
=1.5 V~3.6V)
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
GLQX
t
BE
t
EHQZ
t
GHQZ
t
BDO
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
CE
t
BA
t
OE
t
CLZ
t
OLZ
t
BE
t
CHZ
t
OHZ
t
BDO
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output Low Z
Data Byte Control To Output Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Data Byte Control To Output High Z
Address Chang to Output Change
UC62LV4096-55
Min
55
-
-
Typ
-
-
-
Max
-
55
55
30
-
10
5
10
-
-
-
10
-
-
-
20
20
20
-
-
-
-
30
-
-
UC62LV4096-70
Min
70
-
-
Typ
-
-
-
Max
-
70
70
35
-
10
5
10
-
-
-
10
-
-
-
20
20
20
-
-
-
-
35
-
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0
PAGE
4
Low Power CMOS SRAM
256K X 16
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
UC62LV4096
-55/-70
t
OH
READ CYCLE2
(1,3,4)
CE
t
CLZ (5)
D
OUT
t
CE
t
CHZ (5)
READ CYCLE3
(1,4)
t
RC
ADDRESS
t
AA
OE
t
OE
CE
t
OLZ
t
CLZ (5)
UB/LB
t
BE
D
OUT
NOTES:
1.
2.
3.
4.
5.
6.
WE\ is high in read cycle.
Device is continuously selected when CE\ = VIL
Address valid prior to or coincident with CE\ transition low.
OE\ = VIL.
Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
t
OH
t
OHZ (1,5)
t
CE
t
CHZ (5)
t
BA
t
BDO
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary
Rev. 1.0
PAGE
5
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