0
R
XC18V00 Series of In-System
Programmable Configuration
PROMs
0
DS026 (v3.0) November 12, 2001
0
Product Specification
•
Dual configuration modes
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-
•
•
•
•
•
Serial Slow/Fast configuration (up to 33 MHz)
Parallel (up to 264 Mb/s at 33 MHz)
Features
•
In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
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-
•
•
•
•
Endurance of 20,000 program/erase cycles
Program/erase over full commercial/industrial
voltage and temperature range
5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals
3.3V or 2.5V output capability
Available in PC20, SO20, PC44 and VQ44 packages
Design support using the Xilinx Alliance and
Foundation series software packages.
JTAG command initiation of standard FPGA
configuration
IEEE Std 1149.1 boundary-scan (JTAG) support
Simple interface to the FPGA
Cascadable for storing longer or multiple bitstreams
Low-power advanced CMOS FLASH process
Description
Xilinx introduces the XC18V00 series of in-system program-
mable configuration PROMs (Figure
1).
Initial devices in this
3.3V family are a 4-megabit, a 2-megabit, a 1-megabit, a
512-Kbit, and a 256-Kbit PROM that provide an
easy-to-use, cost-effective method for re-programming and
storing large Xilinx FPGA or CPLD configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
CLK CE
When the FPGA is in Slave-Parallel or SelectMAP Mode, an
external oscillator generates the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROMs DATA (D0-D7) pins.
The data is clocked into the FPGA on the following rising
edge of the CCLK. Neither Slave-Parallel nor SelectMAP
utilize a Length Count, so a free-running oscillator can be
used.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC17V00 one-time programmable Serial PROM family.
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Memory
Address
Data
Serial
or
Parallel
Interface
7
CEO
D0 DATA
(Serial or Parallel
[Slave-Parallel/SelectMAP] Mode)
D[1:7]
Slave-Parallel and
SelectMAP Interface
CF
DS026_01_111201
Figure 1:
XC18V00 Series Block Diagram
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS026 (v3.0) November 12, 2001
Product Specification
www.xilinx.com
1-800-255-7778
1
XC18V00 Series of In-System Programmable Configuration PROMs
R
Pinout and Pin Description
Table 1:
Pin Names and Descriptions (pins not listed are “no connect”)
Pin
Name
D0
Boundary
Scan
Order
4
3
D1
6
5
D2
2
1
D3
8
7
D4
24
23
D5
10
9
D6
17
16
D7
14
13
CLK
0
20-pin
44-pin
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA IN
Each rising edge on the CLK input increments the
internal address counter if both CE is Low and
OE/RESET is High.
When Low, this input holds the address counter
reset and the DATA output is in a high-impedance
state. This is a bidirectional open-drain pin that is
held Low while the PROM is reset. Polarity is NOT
programmable.
When CE is High, this pin puts the device into
standby mode and resets the address counter. The
DATA output pin is in a high-impedance state, and
the device is in low power standby mode.
43
5
3
19
25
12
14
20
9
25
31
14
9
15
7
(1)
27
33
15
Pin Description
D0 is the DATA output pin to provide data for
configuring an FPGA in serial mode.
VQFP
40
44-pin
PLCC
2
SOIC and
PLCC
1
D0-D7 are the output pins to provide parallel data
for configuring a Xilinx FPGA in
Slave-Parallel/SelectMap mode.
29
35
16
42
4
2
OE/
RESET
20
19
18
DATA IN
DATA OUT
OUTPUT
ENABLE
DATA IN
13
19
8
CE
15
15
21
10
2
www.xilinx.com
1-800-255-7778
DS026 (v3.0) November 12, 2001
Product Specification
R
XC18V00 Series of In-System Programmable Configuration PROMs
Table 1:
Pin Names and Descriptions (pins not listed are “no connect”)
(Continued)
Pin
Name
CF
Boundary
Scan
Order
22
21
20-pin
44-pin
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
Pin Description
Allows JTAG CONFIG instruction to initiate FPGA
configuration without powering down FPGA. This is
an open-drain output that is pulsed Low by the
JTAG CONFIG command.
Chip Enable Output (CEO) is connected to the CE
input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High,
AND the internal address counter has been
incremented beyond its Terminal Count (TC) value.
When OE/RESET goes Low, CEO stays High until
the PROM is brought out of reset by bringing
OE/RESET High.
GND is the ground connection.
VQFP
10
44-pin
PLCC
16
SOIC and
PLCC
7
(1)
CEO
11
12
21
27
13
GND
6, 18,
28 &
41
5
3, 12,
24 &
34
11
11
TMS
MODE
SELECT
The state of TMS on the rising edge of TCK
determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50K ohm
resistive pull-up on it to provide a logic “1” to the
device if the pin is not driven.
This pin is the JTAG test clock. It sequences the
TAP controller and all the JTAG test and
programming electronics.
This pin is the serial input to all JTAG instruction
and data registers. TDI has an internal 50K ohm
resistive pull-up on it to provide a logic “1” to the
system if the pin is not driven.
This pin is the serial output for all JTAG instruction
and data registers. TDO has an internal 50K ohm
resistive pull-up on it to provide a logic “1” to the
system if the pin is not driven.
Positive 3.3V supply voltage for internal logic and
input buffers.
Positive 3.3V or 2.5V supply voltage connected to
the output voltage drivers.
5
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT
31
37
17
V
CC
V
CCO
17, 35
& 38
8, 16,
26 &
36
23, 41
& 44
14, 22,
32 &
42
18 & 20
19
Notes:
1. Pin 7 is CF in Serial Mode, D4 in Slave-Parallel Mode for 20-pin packages.
DS026 (v3.0) November 12, 2001
Product Specification
www.xilinx.com
1-800-255-7778
3
XC18V00 Series of In-System Programmable Configuration PROMs
R
Xilinx FPGAs and Compatible PROMs
Table 2
provides a list of Xilinx FPGAs and compatible
PROMs.
Table 2:
Xilinx FPGAs and Compatible PROMs
Device
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV405E
XCV600E
XCV812E
Configuration
Bits
360,160
635,360
1,697,248
2,761,952
4,082,656
5,659,360
7,492,064
10,494,432
15,660,000
21,849,568
29,063,136
559,200
781,216
1,040,096
1,335,840
1,751,808
2,546,048
3,607,968
4,715,616
6,127,744
630,048
863,840
1,442,106
1,875,648
2,693,440
3,430,400
3,961,632
6,519,648
XC18V00
Solution
XC18V512
XC18V01
XC18V02
XC18V04
XC18V04
XC18V04
+ XC18V02
2 of XC18V04
3 of XC18V04
4 of XC18V04
5 of XC18V04
+ XC18V02
7 of XC18V04
XC18V01
XC18V01
XC18V01
XC18V02
XC18V02
XC18V04
XC18V04
XC18V04 +
XC18V512
XC18V04 +
XC18V02
XC18V01
XC18V01
XC18V02
XC18V02
XC18V04
XC18V04
XC18V04
2 of XC18V04
Table 2:
Xilinx FPGAs and Compatible PROMs
Device
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
Configuration
Bits
6,587,520
8,308,992
10,159,648
12,922,336
16,283,712
197,696
336,768
559,200
781,216
1,040,096
1,335,840
630,048
863,840
1,134,528
1,442,016
1,875,648
XC18V00
Solution
2 of XC18V04
2 of XC18V04
3 of XC18V04
4 of XC18V04
4 of XC18V04
XC18V256
XC18V512
XC18V01
XC18V01
XC18V01
XC18V02
XC18V01
XC18V01
XC18V02
XC18V02
XC18V02
Capacity
Devices
XC18V04
XC18V02
XC18V01
XC18V512
XC18V256
Configuration Bits
4,194,304
2,097,152
1,048,576
524,288
262,144
In-System Programming
In-System Programmable PROMs can be programmed indi-
vidually, or two or more can be daisy-chained together and
programmed in-system via the standard 4-pin JTAG proto-
col as shown in
Figure 2.
In-system programming offers
quick and efficient design iterations and eliminates unnec-
essary package handling or socketing of devices. The Xilinx
development system provides the programming data
sequence using either Xilinx JTAG Programmer software
and a download cable, a third-party JTAG development sys-
tem, a JTAG-compatible board tester, or a simple micropro-
cessor interface that emulates the JTAG instruction
sequence. The JTAG Programmer software also outputs
4
www.xilinx.com
1-800-255-7778
DS026 (v3.0) November 12, 2001
Product Specification
R
XC18V00 Series of In-System Programmable Configuration PROMs
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data retention
specifications within this endurance limit.
serial vector format (SVF) files for use with any tools that
accept SVF format and with automatic test equipment.
All outputs are held in a high-impedance state or held at
clamp levels during in-system programming.
Design Security
The Xilinx in-system programmable PROM devices incorpo-
rate advanced data security features to fully protect the pro-
gramming data against unauthorized reading.
Table 3
shows the security setting available.
The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
Table 3:
Data Security Options
Default = Reset
Read Allowed
Program/Erase Allowed
Set
Read Inhibited via JTAG
Erase Allowed
OE/RESET
The ISP programming algorithm requires issuance of a
reset that causes OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx HW-130 device programmer. This provides the
added flexibility of using pre-programmed devices in board
design and boundary-scan manufacturing tools, with an
in-system programmable option for future enhancements
and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 20,000 in-system program/erase
V
CC
GND
(a)
(b)
DS026_02_011100
Figure 2:
In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
IEEE 1149.1 Boundary-Scan (JTAG)
The XC18V00 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required boundary scan instructions, as well as many of the
optional instructions specified by IEEE Std. 1149.1. In addi-
tion, the JTAG interface is used to implement in-system pro-
gramming (ISP) to facilitate configuration, erasure, and
verification operations on the XC18V00 device.
Table 4
lists the required and optional boundary-scan
instructions supported in the XC18V00. Refer to the IEEE
Std. 1149.1 specification for a complete description of
boundary-scan architecture and the required and optional
instructions.
DS026 (v3.0) November 12, 2001
Product Specification
www.xilinx.com
1-800-255-7778
5
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