Preliminary
Datasheet
RJK03N7DPA
30V, 35A, 4.4mΩmax.
Built in SBD N Channel Power MOS FET
High Speed Power Switching
Features
High speed switching
Capable of 4.5 V gate drive
Low drive current
High density mounting
Low on-resistance
Pb-free
Halogen-free
R07DS0788EJ0200
Rev.2.00
Feb 12, 2013
Outline
RENESAS Package code: PWSN0008DE-A
(Package name: WPAK(3F))
5 6 7 8
D D D D
5 6 7 8
4
G
4 3 2 1
1, 2, 3
Source
4
Gate
5, 6, 7, 8 Drain
S S S
1 2 3
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body-drain diode reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
Channel to case thermal impedance
Channel temperature
Storage temperature
Notes: 1. PW
10
s,
duty cycle
1%
2. Value at Tch = 25C, Rg
50
3. Tc = 25C
Symbol
V
DSS
V
GSS
I
D
I
D(pulse)Note1
I
DR
I
AP Note 2
E
AS Note 2
Pch
Note3
ch-c
Note3
Tch
Tstg
Ratings
30
±20
35
140
35
12
14.4
35
3.57
150
–55 to +150
Unit
V
V
A
A
A
A
mJ
W
C/W
C
C
R07DS0788EJ0200 Rev.2.00
Feb 12, 2013
Page 1 of 6
RJK03N7DPA
Preliminary
Electrical Characteristics
(Ta = 25°C)
Item
Drain to source breakdown voltage
Gate to source leak current
Zero gate voltage drain current
Gate to source cutoff voltage
Static drain to source on state
resistance
Forward transfer admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Gate Resistance
Total gate charge
Gate to source charge
Gate to drain charge
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Body–drain diode forward voltage
Body–drain diode reverse recovery
time
Notes: 4. Pulse test
Symbol
V
(BR)DSS
I
GSS
I
DSS
V
GS(off)
R
DS(on)
R
DS(on)
|y
fs
|
Ciss
Coss
Crss
Rg
Qg
Qgs
Qgd
t
d(on)
t
r
t
d(off)
t
f
V
DF
t
rr
Min
30
—
—
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
3.6
4.8
65
1970
340
195
2.0
16
5.6
5.1
3.8
3.7
36.0
11.8
0.42
6.8
Max
—
± 0.5
1
2.5
4.4
6.3
—
2750
—
—
4.0
—
—
—
—
—
—
—
—
—
Unit
V
A
mA
V
m
m
S
pF
pF
pF
nC
nC
nC
ns
ns
ns
ns
V
ns
Test Conditions
I
D
= 10 mA, V
GS
= 0
V
GS
= ±20 V, V
DS
= 0
V
DS
= 24 V, V
GS
= 0
V
DS
= 10 V, I
D
= 1 mA
I
D
= 17.5A, V
GS
= 10 V
Note4
I
D
= 17.5A, V
GS
= 4.5 V
Note4
I
D
= 17.5A, V
DS
= 5 V
Note4
V
DS
= 10 V
V
GS
= 0
f = 1 MHz
V
DD
= 10 V
V
GS
= 4.5 V
I
D
= 35 A
V
GS
= 10 V, I
D
= 17.5A
V
DD
10 V
R
L
= 0.57
Rg = 4.7
I
F
= 2 A, V
GS
= 0
Note4
I
F
=35 A, V
GS
= 0
di
F
/ dt = 500 A/
s
R07DS0788EJ0200 Rev.2.00
Feb 12, 2013
Page 2 of 6
RJK03N7DPA
Preliminary
Main Characteristics
Power vs. Temperature Derating
40
1000
Maximum Safe Operation Area
Channel Dissipation Pch (W)
Drain Current I
D
(A)
30
100
1
m
s
20
10
PW = 10 ms
DC
Op
10
1
Operation in
this area is
limited by R
DS(on)
Tc = 25 °C
1 shot Pulse
1
er
ion
at
0
50
100
150
200
0.1
0.1
10
100
Case Temperature Tc (°C)
Drain to Source Voltage V
DS
(V)
Typical Output Characteristics
50
4.5 V
10 V
50
Typical Transfer Characteristics
V
DS
= 5 V
Pulse Test
Pulse Test
2.7 V
Drain Current I
D
(A)
2.6 V
30
2.5 V
Drain Current I
D
(A)
40
40
30
20
20
10
V
GS
= 2.4 V
10
25°C
Tc = 75°C
–25°C
0
2
4
6
8
10
0
1
2
3
4
5
Drain to Source Voltage V
DS
(V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Gate to Source Voltage V
GS
(V)
Static Drain to Source On State Resistance
vs. Drain Current
100
Drain to Source Saturation Voltage
V
DS(on)
(mV)
200
Pulse Test
150
30
Pulse Test
100
10
I
D
= 20 A
50
10 A
5A
V
GS
= 4.5 V
3
10 V
0
5
10
15
20
1
1
3
10
30
100
300 1000
Gate to Source Voltage V
GS
(V)
Drain Current I
D
(A)
R07DS0788EJ0200 Rev.2.00
Feb 12, 2013
Page 3 of 6
RJK03N7DPA
Static Drain to Source On State Resistance
vs. Temperature
10
Pulse Test
10000
3000
Preliminary
Typical Capacitance vs.
Drain to Source Voltage
Capacitance C (pF)
8
I
D
= 5 A, 10 A, 20 A
Ciss
1000
300
100
30
10
0
Coss
Crss
6
V
GS
= 4.5 V
4
10 V
2
0
–25
5 A, 10 A, 20 A
V
GS
= 0
f = 1 MHz
10
20
30
0
25
50
75
100 125 150
Case Temperature Tc (°C)
Drain to Source Voltage V
DS
(V)
Dynamic Input Characteristics
Drain to Source Voltage V
DS
(V)
50
Reverse Drain Current vs.
Source to Drain Voltage
20
50
Gate to Source Voltage V
GS
(V)
Reverse Drain Current I
DR
(A)
I
D
= 35 A
V
GS
V
DD
= 25 V
10 V
10 V
40
5V
Pulse Test
40
16
30
V
DS
12
30
20
8
20
V
GS
= 0, –5 V
10
V
DD
= 25 V
10 V
0
0
10
20
30
40
50
4
10
0
0
0.4
0.8
1.2
1.6
2.0
Gate Charge Qg (nc)
Source to Drain Voltage V
SD
(V)
Maximum Avalanche Energy vs.
Channel Temperature Derating
25
Avalanche Energy E
AS
(mJ)
20
15
10
5
0
25
50
75
100
125
150
Channel Temperature Tch (°C)
R07DS0788EJ0200 Rev.2.00
Feb 12, 2013
Page 4 of 6
RJK03N7DPA
Normalized Transient Thermal Impedance vs. Pulse Width
3
Preliminary
1
D=1
0.5
0.3
0.2
0.1
0.05
0.0
2
P
DM
PW
T
0.1
0.03
se
1
.0
pul
0
t
ho
1s
D=
PW
T
0.01
1m
10 m
100 m
1
10
Pulse Width PW (S)
Avalanche Test Circuit
Avalanche Waveform
1
2
L
•
I
AP2
•
V
DSS
V
DSS
– V
DD
V
(BR)DSS
I
AP
Rg
D. U. T
V
DD
V
DS
V
DS
Monitor
L
I
AP
Monitor
E
AS
=
I
D
Vin
15 V
0
V
DD
Switching Time Test Circuit
Vin Monitor
D.U.T.
Rg
R
L
V
DS
= 10 V
Vin
Vout
Vin
10 V
Vout
Monitor
Switching Time Waveform
90%
10%
10%
10%
90%
td(on)
tr
90%
td(off)
tf
R07DS0788EJ0200 Rev.2.00
Feb 12, 2013
Page 5 of 6
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
