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PROGRAMMABLE PASSIVE DELAY
LINES
TADL-XX-XX
3 Bit Trimmable Analog Delay Line
- Analog input and output
- All delays digitally programmable
- Delays stable and precise
- 24-pin DIP package (.260 high)
- Available in delays up to 260.5ns
- Offered in 40 delay times with trimming resolution from .5 to 1.5ns
Made in U.S.A.
DESIGN NOTES
The "DIP Series" of Trimmable Analog Delay Lines developed by
Engineered Components Company have been designed to allow for final
delay adjustment during or after installation in a circuit. These Trimmable
Analog Delay Lines incorporate required control circuitry to pick-off analog
signals, and are contained in a 24-pin DIP package. These modules are of
hybrid construction utilizing the proven technologies of active integrated
circuitry and of passive networks utilizing capacitive, inductive and
resistive elements. The MTBF on these modules, when calculated per
MIL-HDBK-217 for a 50°C ground fixed environment, is in excess of 1.5
million hours. The design includes internal termination; no additional
external components are needed to obtain the required delay.
These Trimmable Analog Delay Lines are digitally programmable by the
presence of either a T
²
L "l" or a "0" at each of the programming pins.
Since the input and the output terminals are fixed and the programming is
accomplished only by DC voltage levels, programming may be
accomplished by remote switching or permanent termination of the
appropriate programming pins; the Delay Line may also be programmed
automatically by computer generated data. MUX setup time is 24ns
typical.
The TADL is offered in 40 models with time delays to a maximum of
260.5ns and with trimming step resolution as shown in the Part Number
Table. Programming of final delay is accomplished in 8 delay steps in
accordance with the Truth Table examples that follow. Tolerances on
minimum delay, delay change per step and deviation from programmed
delay are shown in the Part Number Table.
Delay time is measured at the 0 volt level on the leading edge.
Temperature coefficient of delay is less than l00ppm/°C over the operating
temperature range of -40 to +85°C.
The TADL is designed for use with analog input signals between -5 and +5
volts and will reproduce them at the output without inversion. Input
impedance is 100 ±10 ohms. Output impedance is 170 ohms typical. The
-3dB bandwidth is given in the Part Number Table on page 3. In general,
shorter delays will correspond to increased line bandwidth.
These "DIP Series" Trimmable Analog Delay Lines are packaged in a 24-
pin DIP housing, molded of flameproof Diallyl Phthalate per ASTM D 5948,
Type SDG-F and are fully encapsulated in epoxy resin. Leads meet the
solderability requirements of MIL-STD-202, Method 208. Corner standoffs
on the housing provide positive standoff from the printed circuit board to
permit solder-fillet formation and flush cleaning of solder-flux residues for
improved reliability.
Marking consists of manufacturer's name, logo (EC
²
), part number,
terminal identification and date code of manufacture. All marking is applied
by silk screen process using white epoxy paint in accordance with MIL-
STD-130, to meet the permanency of identification required by MIL-STD-
202, Method 215.
[Top]
TEST CONDITIONS
1. All measurements are made at 25°C.
2. Vcc supply voltage is maintained at 5.0V DC.
3. Vee supply voltage is maintained at -5.0V DC.
4. Units with a step zero fixed delay of up to 100ns are tested with a 10
Mhz sine wave. Units with a step zero fixed delay of greater than 100ns
are tested with a 7MHz sine wave.
5. Output is loaded with 100K ohms to ground.
OPERATING SPECIFICATIONS
*Vcc supply voltage: .............
*Vee supply voltage: .............
Vee to Vcc voltage: ..............
Supply current: ..................
4.75 to 5.25V DC
-2.0 to -5.25V DC
10.0V DC max.
<1 mA typical
Input impedance: ................. 100 ohms ±10%
Programming and enable pins:
High level input voltage .........
Low level input voltage ..........
Input leakage current ............
Operating temperature range: .....
Storage temperature: .............
2.0V min.
0.8V max.
1 uA max.
-40 to +85°C.
-55 to +125°C.
*For proper operation of the delay line, analog input voltages should not
exceed the Vee or Vcc supplies.
PART NUMBER TABLE
ø DELAYS AND TOLERANCES (in ns)
*Step
Zero
Delay
Time
5.0 ±.5
7.5 ±.6
10.0 ±.7
12.5 ±.8
15.0 ±.9
17.5 ±1.0
20.0 ±1.1
22.5 ±1.2
25.0 ±1.3
27.5 ±1.4
30 ±1.5
35 ±1.5
40 ±2.0
45 ±2.0
50 ±2.5
55 ±2.5
60 ±2.5
65 ±3.0
70 ±3.0
75 ±3.0
80 ±3.0
85 ±4.0
90 ±4.0
95 ±4.0
100 ±4.0
110 ±4.5
120 ±4.5
130
140
150
160
170
180
190
200
210
220
±5.0
±5.0
±5.5
±5.5
±6.0
±6.5
±7.0
±7.5
±8.0
±8.5
Maximum
Delay
Time (Nom)
8.5
11.0
13.5
16.0
18.5
21.0
23.5
26.0
28.5
31.0
37
42
47
52
57
62
67
72
77
82
87
92
97
102
110.5
120.5
130.5
140.5
150.5
160.5
170.5
180.5
190.5
200.5
210.5
220.5
230.5
240.5
250.5
260.5
Delay
Change
Per Step
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
1.0
1.0
±.4
±.4
±.4
±.4
±.4
±.4
±.4
±.4
±.4
±.4
±.7
±.7
±.7
±.7
±.7
±.7
** Maximum
-3dB
Dev iation From
Bandw idth
Programmed
in Mhz
Delay
±0.5
50
±0.5
47
±0.5
44
±0.5
41
±0.5
38
±0.5
36
±0.5
±0.5
±0.5
±0.5
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
34
32
30
28
26
24
23
22
21
20
19
18
18
17
17
16
15
15
14
14
13
13
12
12
11
11
10
10
9.0
9.0
8.0
8.0
7.0
7.0
Part Number
TADL-5.0-0.5
TADL-7.5-0.5
TADL-10.0-0.5
TADL-12.5-0.5
TADL-15.0-0.5
TADL-17.5-0.5
TADL-20.0-0.5
TADL-22.5-0.5
TADL-25.0-0.5
TADL 27.5-0.5
TADL-30-1.0
TADL-35-1.0
TADL-40-1.0
TADL-45-1.0
TADL-50-1.0
TADL-55-1.0
TADL-60-1.0
TADL-65-1.0
TADL-70-1.0
TADL-75-1.0
TADL-80-1.0
TADL-85-1.0
TADL-90-1.0
TADL-95-1.0
TADL-100-1.5
TADL-110-1.5
TADL-120-1.5
TADL-130-1.5
TADL-140-1.5
TADL-150-1.5
TADL-160-1.5
TADL-170-1.5
TADL-180-1.5
TADL-190-1.5
TADL-200-1.5
TADL-210-1.5
TADL-220-1.5
TADL-230-1.5
TADL-240-1.5
TADL-250-1.5
1.0 ±.7
1.0 ±.7
1.0 ±.7
1.0 ±.7
1.0 ±.7
1.0 ±.7
1.0 ±.7
1.0 ±.7
1.5 ±1.0
1.5 ±1.0
1.5 ±1.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
±1.0
230 ±9.0
240 ±9.5
250 ±10.0
1.5 ±1.0
1.5 ±1.0
1.5 ±1.0
TRUTH TABLE EXAMPLES
3
2
1
TADL-10-0.5
TADL-50-1.0
TADL-100-1.5
ETC.
* Delay at step zero is referenced to the input pin.
**All delay times after step zero are referenced to step zero.
ø Special modules can be readily manufactured to improve accuracies
and/or provide customer specified delay times for specific applications.
0
0
0
10
50
100
0
0
1
.5
1
1.5
0
1
0
1
2
3
0
1
1
1.5
3
4.5
1
0
0
2
4
6
1
0
1
2.5
5
7.5
1
1
0
3
6
9
1
1
1
3.5
7
10.5
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