Product Brief
August 2000
TAPC640
High-Speed Switching ATM Port Controller (APC)
Introduction
The ATM port controller (APC) IC is part of the Agere
Systems, Inc. high-speed switching chip set that
provides a highly integrated, innovative, and com-
plete VLSI solution for implementing the ATM layer
functionality/core of an ATM switch system. The chip
set enables construction of high-performance, fea-
ture rich, and cost-effective asynchronous transfer
mode (ATM) switches, scalable over a wide range of
switching capacities.
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Features
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Provides a comprehensive single-chip solution for
implementing all ATM layer functions needed at an
ATM switch port.
Can be configured in a variety of switching modes
for flexible operation:
— Performs as an ATM switch port card by sup-
porting linear aggregation of up to 622 Mbits/s of
ATM traffic at the physical layer interface (full
duplex).
— Operates as a stand-alone, single-chip 32
×
32
shared memory switch or an N:1 concentrator
(622 Mbits/s total switching).
— Operates in conjunction with another APC as a
2
×
2 (1.2 Gbits/s total switching capacity) dual
APC-based switch (no separate external switch
fabric needed).
Performs ATM layer user network interface (UNI)
and network node interface (NNI) management
functions.
Provides two independently operating full-duplex
UTOPIA II compatible interfaces:
— Controls up to 31 full-duplex multiple physical
layer (MPHY) ports on the physical layer side.
— Allows either UTOPIA interface to operate as
16-bit or 8-bit data.
— Allows any MPHY to be configured as a UNI or
NNI.
Supports up to 64K connections with scalable
external memory:
— Manages virtual connection parameter table in
external memory.
— Optionally performs the ATM Forum compliant
dual leaky-bucket policing for up to 64K VCs.
— Facilitates call setup and tear down through VC
parameter table update via high-performance
microprocessor port.
— Optionally translates or passes the generic flow
control (GFC) field of the egress ATM cell
header for NNI or UNI applications.
— Performs virtual path identifier (VPI)/virtual
channel identifier (VCI) translation for up to 64K
connections on egress while allowing reusability
of same VPI/VCI on different UNIs.
Maintains a variety of optional per-connection, per-
port, and per-device statistics counters in external
memory and on-chip.
Provides dual interfaces to high-speed switching
switch fabrics to facilitate construction of redundant
systems for fault tolerance.
Supports spatial and logical multicasting for up to
32 destination ports on egress (31 MPHY ports
and 1 microprocessor interface port).
Provides a generic 32-bit microprocessor interface
with interrupt.
Supports high-speed read and write direct memory
access (DMA) modes for cell extraction and inser-
tion via the microprocessor interface.
Provides input/output (bidirectional) queue man-
agement for an N
×
N switch fabric for over
100 Gbits/s capacity and up to 31 MPHY ports
and one microprocessor port:
— Queues up to 512K ATM cells in external mem-
ory, organized in a per-VC, fully-shared queue-
ing architecture.
— Supports five traffic classes via novel schedul-
ing algorithms, including a WFQ type scheduler
to provide per-VC QoS assurance.
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TAPC640
High-Speed Switching ATM Port Controller (APC)
Product Brief
August 2000
Features
(continued)
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Implements a flexible, efficient buffer/congestion
management scheme based on a Bell Labs’ pat-
ented adaptive dynamic thresholding (ADT) algo-
rithm:
— Supports selective cell discard and early/partial
packet discard (EPD/PPD).
— Provides capability for minimum buffer reserva-
tions on per-connection, per-class, and per-port
basis.
Performs ATM Forum-compliant available bit rate
(ABR) explicit rate flow control using a Bell Labs’ pat-
ented algorithm. Provides optional support for EFCI
marking as well.
Provides operations, administration, and mainte-
nance (OA&M) Fault Management functions for loop-
back, continuity check, defect indication on all
connections, and performance monitoring on up to
127 connections.
Can be used in conjunction with an external switch
fabric (LUC4AS01 (ASX) and LUC4AC01 (ACE) ICs,
part of the high-speed switching chip set) to provide
a scalable, nonblocking switch solution for over
100 Gbits/s capacity.
Supports bandwidth scalability to OC-48 rates via
use of external PIMUX devices on the PHY layer
side.
Provides an enhanced services interface (ESI) to
support operation of an optional external adjunct
device for comprehensive statistical data collection.
Facilitates circuit board testing with on-chip
IEEE*
boundary scan.
Fabricated as a low-power, monolithic IC in submi-
cron 0.25 µm, 3.3 V CMOS technology, with 5 V tol-
erant and TTL-level compatible I/O.
Available in a 600-pin LBGA package.
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Applications
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ATM switches
x-DSL systems
DLC systems
ADM
Access multiplexers
Routers
PBX
Wireless infrastructure equipment
VP rings
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*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
2
Agere Systems Inc.
Product Brief
August 2000
TAPC640
High-Speed Switching ATM Port Controller (APC)
Description
Block Diagram
Figure 1 presents a block diagram of the APC chip. Each high-level block function is summarized in this section.
CRAM
CONTROL
MEMORY
VCRAM
VC TABLES
MEMORY
PRAM
POINTER
MEMORY
BRAM
CELL BUFFER
MEMORY
HLX
HEADER LOOK-UP
AND TRANSLATION
VCT
VIRTUAL
CONNECTION
TABLE MEMORY I/F
APC IC
GCR
POLICING
GCR/BMX
THRESHOLDING
BRI
CELL BUFFER/POINTER
MEMORY INTERFACE
SXI
UPI
UTOPIA 2+
(PORT A)
TO/FROM
MPHY DEVICES
UTOPIA
INTERFACE
A
UTOPIA 2+
(PORT B)
UTOPIA
INTERFACE
B
SOX/NMX
STATISTICS AND
OAM CONTROLLER
iQSC
INGRESS QUEUE
SCHEDULER
FABRIC
INTERFACE
B
PORT B
AFE/XRE
ABR FLOW
CONTROL ENGINE
eQSC
EGRESS QUEUE
SCHEDULER
MPI
MICROPROCESSOR I/F
AND CONFIG. REGISTERS
TCT
TIME
COUNTER
WCK
WORLD
CLOCK
ESI
ENHANCED
SERVICE
INTERFACE
RST
RESET
DRIVERS
JTG
TEST ACCESS
PORT AND SCAN
CONTROLLER
MICROPROCESSOR
SYNCHRONIZATION
PULSE
SYSTEM
CLOCK
ADJUNCT
DEVICE
SYSTEM
RESET
SYSTEM
TEST
SSRAM
SDRAM
5-8009(F)r.2
Figure 1. High-Level Block Diagram of the APC IC
Agere Systems Inc.
TO/FROM AN
ATLANTA
™ FABRIC
FABRIC
INTERFACE
A
PORT A
3
TAPC640
High-Speed Switching ATM Port Controller (APC)
Product Brief
August 2000
Description
(continued)
UTOPIA Interface (UPI)
The UPI controls the transfer of ATM cells between the
APC and multiple physical layer devices (MPHYs) con-
nected to it, via two full-duplex UTOPIA Level II com-
patible interfaces operating independently at up to
52 MHz.
The UPI supports linear aggregation of ATM traffic up
to 622 Mbits/s. Each UTOPIA interface can be enabled
independently and is always a bus master. Receive
parity checking can be enabled or disabled. Transmit
parity generation can be configured as odd or even.
Each transmit interface can be configured to internally
loopback cells to its receive interface independently for
diagnostic purposes.
Additionally, the UPI can support an extended cell for-
mat and an external port inverse multiplexer (PIMUX)
device to interface with link rates greater than
622 Mbits/s such as OC-48 trunks.
Each interface can be independently configured to
operate in 16-bit or 8-bit mode (for UTOPIA Level 1
compatibility), with a standard or extended cell format
and its own contiguous UTOPIA poll address range to
support up to 31 MPHY devices*.
For special cells (OA&M and RM), the UPI also checks
(on receive) and inserts (on transmit) the payload CRC-
10 field.
Virtual Connection Table Memory Interface
(VCT)
The VCT handles all the necessary operations needed
to read, write, and refresh the ingress and egress vir-
tual connection parameter tables, maintained in exter-
nal SDRAM (VCRAM) for up to 64K connections.
Policing Generic Cell Rate (GCR)
The GCR implements two instances of the generic cell
rate algorithm (GCRA) for each connection to police
cells for conformance to their negotiated traffic con-
tracts. It uses the virtual scheduling algorithm outlined
in ITU-T I.371 to determine conformance. Seven possi-
ble policing configurations are supported for each
GCRA instance including all the conformance defini-
tions specified in ATM Forum Traffic Management
Specification Version 4.0.
Policing can be enabled or disabled on a per-connec-
tion basis, or globally enabled or disabled. The policing
action, monitor, tag, or drop can be programmed sepa-
rately for each individual leaky bucket on a per-connec-
tion basis. The range of policed rates goes from
424 bits/s (one cell per second) to the maximum sup-
ported rate of 622 Mbits/s.
Buffer Management Controller (BMX)
The GCRBMX block performs buffer management
functions, by checking a variety of per-connection, per-
port, and per-traffic class thresholds. They are used to
drop a cell before it is queued.
A CLP0+1 discard threshold, an optional CLP1 discard
threshold, and an optional early packet discard (EPD)
threshold are provided for each connection on ingress
and egress. These thresholds can be configured as
static or dynamic.
The dynamic threshold is based on an effective buffer
allocation for the connection. This allocation is not used
directly as the discard threshold. The overall reserve
and specific congestion conditions add to or subtract
from the buffer allocation to continuously adjust the
threshold. These adjustments are based on the avail-
able reserve of the common buffer pool and the con-
gestion threshold established for the traffic class to
which the connection belongs. This balances the
losses of the given circuit against the overall state of
the system. A guaranteed minimum buffer space is
supported during periods of heavy buffer use.
Header Look-Up and Control Memory Inter-
face (HLX)
The HLX performs a three-level ingress look-up and
one-level egress look-up in external memory to fetch
connection information for up to 64K ingress and
egress connections. The HLX supports MPHY port
configuration (UNI or NNI), VP or VC switching, ATM
header validation, ingress cell capture and cell recogni-
tion (e.g., RM and OA&M cells).
Additionally, the HLX accesses control memory tables
maintained in external synchronous static memory,
SSRAM (CRAM), to support queuing, scheduling
(QSC), and OA&M (NMXSOX) operations.
* Only 31 MPHY devices can be supported over the two UTOPIA interfaces
combined.
4
Agere Systems Inc.
Product Brief
August 2000
TAPC640
High-Speed Switching ATM Port Controller (APC)
uler. The third (port merge) level of the hierarchy
merges the CBR VC scheduler and the two class
schedulers together.
The CBR scheduler uses a non-work-conserving
shaped virtual clock (ShVC) algorithm to shape CBR
virtual connections to any one of up to 32 user-pro-
grammable rates.
The rt-VBR scheduler uses a work-conserving starting
potential fair queuing (SPFQ) algorithm to schedule vir-
tual connections using any one of up to 16 user-pro-
grammable rates/weights.
nrt-VBR, ABR, and UBR schedulers each use a work-
conserving variable length frame based weighted
round-robin (WRR) algorithm to schedule virtual con-
nections using one of up to 256K different weights.
The guaranteed traffic class scheduler (GTS) uses the
ShVC algorithm to provide guaranteed bandwidth to
each of four classes (the rt-VBR, nrt-VBR, ABR, and
UBR VC schedulers). A user-programmable rate is
provided for each class.
The excess bandwidth class scheduler (EBS) uses a
work-conserving self-clocked fair queuing (SCFQ)
algorithm to fairly allocate excess bandwidth to each of
four classes (the rt-VBR, nrt-VBR, ABR, and UBR VC
schedulers). A user-programmable weight is provided
for each class.
The port merge scheduler merges the CBR VC sched-
uler and the GTS class scheduler together with strict
priority over the EBS class scheduler. CBR and GTS
service is arbitrated at this level using timestamps.
Description
(continued)
Buffer Management Controller (BMX)
(continued)
The buffer is logically partitioned so that each traffic
class can support a different buffer reservation inde-
pendent of other classes. Additional mechanisms are
provided to control the sharing of buffers between ports
with minimum guarantees for each port.
An optional partial packet discard (PPD) mode is sup-
ported for each connection. A static selective explicit
forward congestion indicator (SEFCI) marking thresh-
old is also provided. EFCI marking can be selectively
enabled for each connection.
Cell Buffer Memory Interface (BRI)
The BRI handles all the necessary operations needed
to read, write, and refresh the cell data in ingress and
egress cell buffer pools maintained in external SDRAM
(BRAM). The BRI supports up to 512K cell buffers
which can be statically partitioned between ingress
and egress without restriction. The BRI performs cell
enqueue and dequeue operations and serves also as
intermediate cell storage to support NMXSOX and
XREAFE operations.
Additionally, the BRI manages the communication
between the APC and the ingress and egress cell
pointer memory maintained in external SDRAM
(PRAM).
Ingress Queue Scheduler (iQSC)
The iQSC implements a sophisticated per virtual con-
nection queue architecture and hierarchical scheduling
algorithms for ingress.
The iQSC performs the virtual connection enqueue and
dequeue operations, which are supported by the HLX,
VCT, and BRI blocks.
The iQSC provides novel scheduling algorithms to ser-
vice up to 64K VC queues and five traffic classes
(CBR, rt-VBR, nrt-VBR, ABR, and UBR) using a three-
level hierarchy. The first (VC) level of the hierarchy
contains per-VC schedulers for each of the five traffic
classes. Each VC scheduler can support all 64K VC
queues as needed. The second (class) level of the
hierarchy contains two class schedulers: one to pro-
vide guaranteed bandwidth and one to distribute
excess bandwidth to each work-conserving VC sched-
Switch Fabric Interface (SXI)
The SXI implements an interface to
ATLANTA
switch
fabrics, as well as a loopback mode for a single APC
stand-alone operation. The SXI interface consists of an
8-bit parallel data bus plus additional control signals
and clock, operating at up to 100 MHz. The SXI termi-
nates the simple
ATLANTA
fabric interface protocol.
The transmit interface can be configured to generate
odd or even parity. The receive interface checks for
odd parity and protocol violations. It also extracts the
fabric backpressure information from the cell header.
This interface is duplicated to allow construction of
redundant switch fabric architectures for fault toler-
ance, and 1.2 Gbits/s fabric-less switches using two
APCs. Each transmit interface can be independently
enabled and disabled.
Agere Systems Inc.
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