application
INFO
available
UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
1V Synchronous Boost Converter
FEATURES
•
1V Input Voltage Operation Startup
Guaranteed Under Full Load on Main
Output With Operation Down to 0.4V
•
Input Voltage Range of 1V to V
OUT
+
0.5V
•
500mW Output Power at Battery
Voltages as Low as 0.8V
•
Secondary 9V Supply From a Single
Inductor
•
•
•
•
DESCRIPTION
The UCC3941 family of low input voltage single inductor boost converters
are optimized to operate from a single or dual alkaline cell, and step up to
a 3.3V, 5V, or an adjustable output at 500mW. The UCC3941 family also
provides an auxiliary 9V 100mW output, primarily for the gate drive supply,
which can be used for applications requiring an auxiliary output such as a
5V supply by linear regulating. The primary output will start up under full
load at input voltages typically as low as 0.8V, with a guaranteed maximum
of 1V, and will operate down to 0.4V once the converter is operating, maxi-
mizing battery utilization.
Demanding applications such as Pagers and PDA’s require high efficiency
Adjustable Output Power Limit Control
from several milli-watts to several hundred milli-watts, and the UCC3941
family accommodates these applications with >80% typical efficiencies
Output Fully Disconnected in
over the wide range of operation. The high efficiency at low output current
Shutdown
is achieved by optimizing switching and conduction losses along with low
quiescent current. At higher output current the 0.25Ω switch, and 0.4Ω syn-
Adaptive Current Mode Control for
chronous rectifier, along with continuous mode conduction, provide high ef-
Optimum Efficiency
ficiency. The wide input voltage range on the UCC3941 family can
8µA Shutdown Supply Current
accommodate other power sources such as NiCd and NiMH.
Other features include maximum power control and shutdown control.
Packages available are the 8-pin SOIC (D) and 8-pin DIP (N or J).
SIMPLIFIED BLOCK DIAGRAM AND APPLICATION CIRCUIT
+
22µH
10µF
0.8V TO VOUT +0.5V
VIN
SW
3
8V
VGD
8
0.4Ω
UCC3941-3 = 3.3V
UCC3941-5 = 5.0V
UCC3941-ADJ = 1.30V TO 6V
VOUT
2
10µF
STARTUP
CIRCUITRY
0.25Ω
1
100µF
PLIM
SD
5
4
OPEN=SD
*SGND/FB
–
+
UCC3941-ADJ
1.25V
6
PGND
*FOR UCC3941-ADJ ONLY:
PIN 7 = SGND & PGND, PIN 6 = OUTPUT SENSE FEEDBACK, FB.
7
UDG-98147
SLUS242 - JULY 1999
FOR UCC3941-ADJ ONLY
MODULATOR CONTROL CIRCUIT
SYNCHRONOUS RECTIFICATION CIRCUITRY
ANTI-CROSS CONDUCTION
STARTUP
MULTIPLEXING LOGIC
MAXIMUM INPUT POWER CONTROL
ADAPTIVE CURRENT CONTROL
UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
VIN Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V
SD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VIN
PLIM Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V
VGD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 15V
SW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 15V
VOUT Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
DIL-8, SOIC-8 (Top View)
N or J Package, D Package
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.
Pin 6 is FB for UCC3941-ADJ.
ELECTRICAL CHARACTERISTICS:
Unless otherwise specified, for UCC3941, T
A
= 0°C to 70°C; for UCC2941, T
A
= –40°C
to 85°C; VIN = 1.25V, T
A
= T
J
.
PARAMETER
VIN Section
Minimum Startup Voltage
Minimum Start Voltage
Minimum Startup Voltage
Minimum Dropout Voltage
Input Voltage Range
Quiescent Supply Current
Supply Current at Shutdown
Output Section
Quiescent Supply Current
Supply Current at Shutdown
Regulation Voltage (UCC3941-3)
Regulation Voltage (UCC3941-5)
FB Voltage (UCC3941-ADJ)
VGD Output Section
Quiescent Supply Current
Supply Current at Shutdown
Regulation Voltage
(Note 2)
SD = Open
1V < VIN < 3V
1V < VIN < 3V, 0mA < I
OUT
< 10mA (Note 1)
Inductor Charging Section (L = 22µH)
Peak Discontinuous Current
Peak Continuous Current
Over Operating Range
R
PLIM
= 6.2Ω, UCC3941-3 and UCC3941-5
UCC3941-ADJ
0.5
0.6
0.50
0.8
0.9
0.85
1.1
1.3
A
A
A
7.5
7.4
25
8
8.7
8.7
60
20
9.2
9.3
µA
µA
V
V
(Note 2)
SD = Open
1V < VIN < 3V
1V < VIN < 3V, 0mA < I
OUT
< 150mA (Note 1)
1V < VIN < 5V
1V < VIN < 5V, 0mA < I
OUT
100mA (Note 1)
1V < VIN < 3V
3.18
3.17
4.85
4.8
1.212
32
6
3.25
3.30
5.00
5.0
1.250
80
15
3.37
3.43
5.15
5.2
1.288
µA
µA
V
V
V
V
V
(Note 2)
SD = Open
No External VGD Load, T
J
= 25°C, I
OUT
= 100mA (Note 1)
No External VGD Load, I
OUT
= 100mA, T
J
= 0° C to 85° C
(Note 1)
No External VGD Load, T
J
= –40°C to 0° C
No External VGD Load, I
OUT
= 100mA, VGD = 6.3V
(Note 1)
1
13
8
0.8
0.9
0.9
1.0
1.1
1.5
0.5
VOUT
+0.5
25
20
V
V
V
V
V
µA
µA
TEST CONDITIONS
MIN
TYP
MAX UNITS
2
UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
ELECTRICAL CHARACTERISTICS:
Unless otherwise specified, for UCC3941, T
A
= 0°C to 70°C; for UCC2941, T
A
= –40°C
to 85°C; VIN = 1.25V, T
A
= T
J
.
PARAMETER
Inductor Charging Section
Charge Switch R
DS(on)
Current Limit Delay
Synchronous Rectifier Section
Rectifier R
DS(on)
N and D Package, I = 200mA, UCC3941-ADJ V
OUT
= 3.3V
and UCC3941–3
N and D Package, I = 200mA, UCC3941-5
Shutdown Section
Shutdown Bias Current
–10
–7
µA
0.35
0.5
0.6
0.8
Ω
Ω
N and D Package, I = 200mA
(Note 1)
0.25
50
0.4
Ω
ns
TEST CONDITIONS
MIN
TYP
MAX UNITS
Note 1:
Performance from application circuit shown in Figures 3 - 5 guaranteed by design and alternate testing methods, but not
100% tested as shown in production.
Note 2:
For the UCC3941-3, VOUT = 3.47V and VGD = 9.3V. For the UCC3941-5, VOUT = 5.25V, VGD = 9.3V. For the UCC3941-
ADJ, FB = 1.315V, VGD = 9.3V.
PIN DESCRIPTIONS
FB:
Feedback control pin used in the UCC3941-ADJ
version only. The internal reference for this comparator is
1.25V and external resistors provide the gain to the
output voltage.
PGND:
Power ground of the IC. The inductor charging
current flows through this pin. For the UCC3941-ADJ
signal ground and power ground lines are tied to a
common pin.
PLIM:
This pin is programmed to set the maximum input
power for the converter. For example a 1A current limit at
1V would have a 333mA limit at 3V input keeping the
input power constant at 1W. The peak current at VIN =
1V is programmed to 1.5A (1.5W) when this pin is
grounded. The power limit is given by:
SGND:
Signal ground of the IC. For the UCC3941-ADJ
signal ground and power ground lines are tied to a
common pin.
SW:
An inductor is connected between this node and
VIN. The VGD (Gate Drive Supply) flyback diode is also
connected to this pin. When servicing the 3.3V supply,
this pin will go low charging the inductor, then shut off,
dumping the energy through the synchronous rectifier to
the output. When servicing the VGD supply, the internal
synchronous rectifier stays off, and the energy is diverted
to VGD through the flyback diode. During discontinuous
portions of the inductor current a MOSFET resistively
connects VIN to SW damping excess circulating energy
to eliminate undesired high frequency ringing.
VGD:
The VGD pin which is coarsely regulated around
9V and is primarily used for the gate drive supply for the
power switches in the IC. This pin can be loaded with up
to 10mA as long as it does not present a load at voltages
below 2V. This ensures proper startup of the IC. The
VGD supply can go as low as 7.5V without interfering
with the servicing of the 3.3V output. Below 7.5V, VGD
will have the highest priority, although practically the
voltage should not decay to that level if the output
capacitor is sized properly.
VIN:
Input voltage to supply the IC during startup. After
the output is running the IC draws power from VOUT or
VGD.
VOUT:
Main output voltage (3.3V, 5V or adjustable)
which has highest priority in the multiplexing scheme, as
long as VGD is above the critical level of 7.5V. Loads
over 150mA are achievable at 1V input voltage. This
output will startup with 1V input at full load.
PL
(
W
)
=
11.8
•
n
+
V
(0 . 26 )
R
PL
+
6.7
IN
where R
PL
is equal to the external resistor from the PLIM
pin to ground and
n
is the expected efficiency of the
converter. The peak current limit is given by:
I
PK
(
A
)
=
V
IN
•
(
R
PL
+
6.7
)
11.8
•
n
+
0 . 26
Constant power gives several advantages over constant
current such as lower output ripple.
SD:
When this pin is open, the built in 7µA current source
pulls up on the pin and programs the IC to go into
shutdown mode. This pin requires an open circuit for
shutdown and will not operate correctly when driven to a
logic level high with TTL or CMOS logic. When this pin is
connected to ground, (either directly or with a transistor)
the IC is enabled and both output voltages will regulate.
3
UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
APPLICATION INFORMATION
A detailed block diagram of the UCC3941 is shown in
Fig. 1. Unique control circuitry provides high efficiency
power conversion for both light and heavy loads by tran-
sitioning between discontinuous and continuous conduc-
tion based on load conditions. Fig. 2 depicts converter
waveforms for the application circuit shown in Fig. 3. A
single 22µH inductor provides the energy pulses required
for a highly efficient 3.3V converter at up to 500mW out-
put power.
VIN
3
ANTI-RINGING
SWITCH
SW
8
1
VGD
VGD
2
200kHz
STARTUP
OSCILATOR
AND CONTROL
VGD ZERO
DETECT
VGD
+
–
+
5V
–
FROM
SD
RECTIFIER
CONTROL
FROM SD
VOUT ZERO
DETECT
–
+
1.7µS
OFF TIME
CONTROLLER
VGD
VOUT
1.4A
5Ω MAX
PLIM
5
CURRENT
LIMIT
+
50mV
MAXIMUM
SD
SD
4
50mV
VIN
–
VSAT
VIN
ON TIME
CONTROLLER
11µSEC
T
ON
=
VIN
R
SD
BOOST
LATCH
Q
CLK
D
L1
Q
–
+
Q
R
SD
THERMAL
SHUTDOWN
–
+
* 3.3V FOR UCC3941-3
5.0V FOR UCC3941-5
1.25V FOR UCC3941-ADJ
** 8.7V FOR UCC3941-3
9.6V FOR UCC3941-5/-ADJ
*** 7.7V FOR UCC3941-3
8.8V FOR UCC3941-5/-ADJ
***
VGD
–
+
**
VGD
*
6
FB FOR
UCC3941-ADJ
ONLY
6
SGND FOR
UCC3941-3/-5
7
PGND
Note: Switches are shown in the logic low state.
UDG-98146
Figure 1. 1V Synchronous boost.
4
UCC2941-3/-5/-ADJ
UCC3941-3/-5/-ADJ
APPLICATION INFORMATION (cont.)
UDG-96117
Figure 2. Inductor current and output ripple waveforms.
At time
t
1
, the 3.3V output drops below its lower thresh-
old, and the inductor is charged with an on time deter-
mined by:
T
ON
=
12
µ
s
VIN
For a 1.25V input, and a 22µH inductor, the resulting
peak current is approximately 500mA. At time
t
2
, the in-
ductor begins to discharge with a minimum off time of
1.7µs. Under lightly loaded conditions, the amount of en-
ergy delivered in this single pulse would satisfy the volt-
age control loop, and the converter would not command
any more energy pulses until the output again drops be-
low the lower voltage threshold.
At time
t
3
, the VGD supply has dropped below its lower
threshold, but the output voltage is still above its thresh-
old point. This results in an energy pulse to the gate drive
supply at
t
4
. However, while the gate drive is being serv-
iced, the output voltage has dropped below its lower
threshold, so the state machine commands an energy
pulse to the output as soon as the gate drive pulse is
completed.
Time
t
6
, represents a transition between light and heavy
load. A single energy pulse is not sufficient to force the
output voltage above its upper threshold before the mini-
mum off time has expired, and a second charge cycle is
commanded. Since the inductor current does not reach
zero in this case, the peak current is greater than 0.5A at
the end of the next charge on time. The result is a
ratcheting of inductor current until either the output volt-
age is satisfied, or the converter reaches its programmed
current limit. At time
t
7
, the gate drive voltage has
dropped below its threshold but the converter continues
to service the output because it has highest priority, un-
less VGD drops below 7.5V.
Between
t
7
and
t
8
, the converter reaches its peak current
limit which is determined by R
PL
and VIN. Once the limit
is reached, the converter operates in continuous mode
with approximately 200mA of ripple current. At time
t
8
,
the output voltage is satisfied, and the converter can ser-
vice VGD, which occurs at
t
9
.
5
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