A5821
BiMOS II 8-Bit Serial Input Latched Drivers
Last Time Buy
These parts are in production but have been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: May 2, 2005
Deadline for receipt of LAST TIME BUY orders: October 28, 2005
Recommended Substitutions:
For new customers or new applications, refer to the
A6821.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.
5821
BiMOS II 8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A merged combination of bipolar and MOS technology gives
these devices an interface flexibility beyond the reach of standard
logic buffers and power driver arrays. The UCN5821A and
UCN5821LW each have an eight-bit CMOS shift register and
CMOS control circuitry, eight CMOS data latches, and eight
bipolar current-sinking Darlington output drivers.
BiMOS II devices have much higher data-input rates than the
original BiMOS circuits. With a 5 V logic supply, they will
typically operate at better than 5 MHz. With a 12 V supply,
significantly higher speeds are obtained. The CMOS inputs are
compatible with standard CMOS and NMOS logic levels. TTL
circuits may require the use of appropriate pull-up resistors. By
using the serial data output, the drivers can be cascaded for
interface applications requiring additional drive lines.
The UCN5821A are furnished in a standard 16-pin plastic
DIP; the UCN5821LW are in a 16-lead wide-body SOIC for sur-
face-mount applications. The UCN5821A is also available for
operation from -40°C to +85°C. To order, change the prefix from
‘UCN’ to ‘UCQ’.
Data Sheet
26185.12F
CLOCK
SERIAL
DATA IN
LOGIC
GROUND
LOGIC
SUPPLY
SERIAL
DATA OUT
STROBE
OUTPUT
ENABLE
POWER
GROUND
1
2
3
4
5
6
7
8
CLK
16
15
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
SHIFT REGISTER
14
LATCHES
V
DD
13
12
11
10
9
ST
OE
SUB
Dwg. PP-026A
Note the DIP package and the SOIC package are
electrically identical and share common terminal
number assignments.
ABSOLUTE MAXIMUM RATINGS
at 25
°
C Free-Air Temperature
Output Voltage, V
OUT
.....................
50 V
Logic Supply Voltage, V
DD
.............
15 V
Input Voltage Range,
V
IN
..................
-0.3 V to V
DD
+ 0.3 V
Continuous Output Current,
I
OUT
.....................................
500 mA
Package Power Dissipation, P
D
Package Code ‘A’ ..................
2.1 W
Package Code ‘LW’ ...............
1.5 W
Operating Temperature Range,
T
A
............................ -20
°
C to +85
°
C
Storage Temperature Range,
T
S
.......................... -55
°
C to +150
°
C
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
FEATURES
s
To 3.3 MHz Data Input Rate
s
CMOS, NMOS, TTL Compatible
s
Internal Pull-Down Resistors
s
Low-Power CMOS Logic & Latches
s
High-Voltage Current-Sink Outputs
s
Automotive Capable
Always order by complete part number, e.g.,
UCN5821A
.
www.allegromicro.com
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
V
DD
CLOCK
SERIAL
DATA IN
LOGIC
GROUND
1
FUNCTIONAL BLOCK DIAGRAM
V
DD
4
LOGIC
SUPPLY
SERIAL
DATA OUT
STROBE
OUTPUT ENABLE
(ACTIVE LOW)
2
SERIAL-PARALLEL SHIFT REGISTER
5
3
LATCHES
6
IN
7
STROBE &
OUTPUT
ENABLE
16
15
14
13
12
11
10
9
MOS
BIPOLAR
8
POWER
GROUND
Dwg. FP-013A
SUB
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
Dwg. EP-010-3
NOTE — There is an indeterminate resistance between logic ground and power
ground. For proper operation, these terminals must be externally connected
together.
VDD
CLOCK &
SERIAL
DATA IN
IN
Number of Outputs ON
(I
OUT
= 200 mA
V
DD
= 12 V)
8
7
6
5
4
3
2
1
UCN5821A Max. Allowable Duty Cycle
at Ambient Temperature of
25
°
C
40
°
C
50
°
C
60
°
C
70
°
C
90%
100%
100%
100%
100%
100%
100%
100%
79%
90%
100%
100%
100%
100%
100%
100%
72%
82%
96%
100%
100%
100%
100%
100%
65%
74%
86%
100%
100%
100%
100%
100%
57%
65%
76%
91%
100%
100%
100%
100%
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
OUT
Number of Outputs ON
(I
OUT
= 200 mA
V
DD
= 12 V)
8
7
6
5
4
3
2
1
UCN5821LW Max. Allowable Duty Cycle
at Ambient Temperature of
25
°
C
40
°
C
50
°
C
60
°
C
70
°
C
67%
77%
90%
100%
100%
100%
100%
100%
59%
68%
79%
95%
100%
100%
100%
100%
54%
62%
72%
86%
100%
100%
100%
100%
49%
56%
65%
78%
98%
100%
100%
100%
43%
49%
57%
68%
86%
100%
100%
100%
7.2K
3K
SUB
Dwg. No. A-14,314
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2004 Allegro MicroSystems, Inc.
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at T
A
= +25
°
C, V
DD
= 5 V (unless otherwise specified).
Limits
Characteristic
Output Leakage
Current
Collector-Emitter
Saturation Voltage
V
CE(SAT)
Symbol
I
CEX
V
OUT
= 50 V
V
OUT
= 50 V, T
A
= +70°C
I
OUT
= 100 mA
I
OUT
= 200 mA
I
OUT
= 350 mA, V
DD
= 7.0 V
Input Voltage
V
IN(0)
V
IN(1)
V
DD
= 12 V
V
DD
= 5.0 V
Input Resistance
r
IN
V
DD
= 12 V
V
DD
= 5.0 V
Supply Current
I
DD(ON)
One Driver ON, V
DD
= 12 V
One Driver ON, V
DD
= 10 V
One Driver ON, V
DD
= 5.0 V
I
DD(OFF)
V
DD
= 5.0 V, All Drivers OFF, All Inputs = 0 V
V
DD
= 12 V, All Drivers OFF, All Inputs = 0 V
Test Conditions
Min.
—
—
—
—
—
—
10.5
3.5
50
50
—
—
—
—
—
Max.
50
100
1.1
1.3
1.6
0.8
—
—
—
—
4.5
3.9
2.4
1.6
2.9
Units
µA
µA
V
V
V
V
V
V
kΩ
kΩ
mA
mA
mA
mA
mA
www.allegromicro.com
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
Serial Data present at the input is
transferred to the shift register on the
logic “0” to logic “1” transition of the
CLOCK input pulse. On succeeding
CLOCK pulses, the registers shift data
information towards the SERIAL DATA
OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge
of the CLOCK input waveform.
G
CLOCK
A
B
DATA IN
E
C
STROBE
F
D
OUTPUT
ENABLE
OUT
N
Dwg. No. A-12,627
TIMING CONDITIONS
(V
DD
= 5.0 V, T
A
= +25
°
C, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................
75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) ...........................................................................
75 ns
C.
Minimum Data Pulse Width ..............................................................
150 ns
D.
Minimum Clock Pulse Width ............................................................
150 ns
E.
F.
Minimum Time Between Clock Activation and Strobe .......................
30 ns
Minimum Strobe Pulse Width ...........................................................
100 ns
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel con-
version). The latches will continue to
accept new data as long as the STROBE
is held high. Applications where the
latches are bypassed (STROBE tied high)
will require that the ENABLE input be
high during serial data entry.
When the ENABLE input is high, all
of the output buffers are disabled (OFF)
without affecting the information stored
in the latches or shift register. With the
ENABLE input low, the outputs are
controlled by the state of the latches.
G.
Typical Time Between Strobe Activation and
Output Transition ..........................................................................
1.0
µ
s
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I
1
I
2
I
3
.............. I
8
H
L
X
H
L
R
1
R
2
.............. R
7
R
1
R
2
.............. R
7
X
X
.............. X
Serial
Data Strobe
Output Input
R
7
R
7
R
8
X
P
8
L
H
R
1
R
2
R
3
.............. R
8
P
1
P
2
P
3
.............. P
8
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
X
X
.............. X
L
H
P
1
P
2
P
3
..............
H H H ..............
P
8
H
Latch Contents
I
1
I
2
I
3
.............. I
8
Output
Enable
Output Contents
I
1
I
2
I
3
..............
I
8
R
1
R
2
R
3
.............. R
8
X
P
1
P
2
P
3
.............. P
8
P = Present State
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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