MDT10P621N(AB)
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static
CMOS technology process to achieve higher speed and
smaller size with the low power consumption and high
noise immunity. On chip memory includes 4K words of
ROM, and 192 bytes of static RAM.
-CCP,SCM
TMR0 : 8-bit real time clock/counter
TMR1 : 16-bit real time clock/count
TMR2 : 8-bit clock/counter(internal)
4 types of oscillator can be selected by
programming option:
RC-Low cost RC oscillator
2. Features
The followings are some of the features on the hardware
and software :
Fully CMOS static design
8-bit data bus
On chip EPROM size : 4.0 K words
Internal RAM size : 224 bytes
(192 general purpose registers, 32 special
registers)
37 single word instructions
14-bit instructions
8-level stacks
Operating voltage : 2.5 V ~ 5.5 V (PRD Disable)
V ~ 5.5 V (PRD Enable)
Operating frequency : DC ~ 20 MHz
The most fast execution time is 200 ns under 20
MHz in all single cycle instructions except the
branch instruction
Addressing modes include direct, indirect and
relative addressing modes
Power-on Reset
Power edge-detector Reset (2.1V)
Power range-detector Reset
Sleep Mode for power saving
Capture,Compare,PWM module
Synchronous serial port with SCM
7 interrupt sources:
-External INT pin
-TMR0 timer,TMR1 timer,TMR2 timer
-PortB<7:4> interrupt on change
LFXT-Low frequency crystal oscillator
XTAL-Standard crystal oscillator
HFXT-High frequency crystal oscillator
On-chip RC oscillator based Watchdog
Timer(WDT)
22 I/O pins with their own independent direction
control
3. Applications
The application areas of this MDT10P621N range from
appliance motor control and high speed auto-motive to
low
power
remote
transmitters/receivers,
pointing
4.5 devices, and telecommunications processors, such as
Remote controller, small instruments, chargers, toy,
automobile and PC peripheral … etc.
This specification are subject to be changed without notice. Any latest information
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P.1
2008/7 Ver1.0
MDT10P621N(AB)
4. Pin Assignment
/MCLR 1
PA0 2
PA1 3
PA2 4
PA3 5
PA4/RTCC 6
PA5/SS 7
V
ss
8
OSC1/CLKIN 9
OSC2/CLKOUT 10
PC0/T1OSO/T1CKI 11
PC1/T1OSI 12
PC2/CCP 13
PC3/SCK 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0/INT
V
dd
V
ss
PC7
PC6
PC5/SDO
PC4/SDI
5. Pin Function Description
Pin Name
PA0~PA3,PA5
RTCC/PA4
I/O
I/O
I/O
Port A, TTL input level
Real Time Clock/Counter, Schmitt Trigger input level
Open drain output
PB0~PB7
I/O
Port B, TTL input level / PB0:External interrupt input ,
PB4~PB7:Interrupt on pin change
PC0~PC7
/MCLR
OSC1/CLKIN
OSC2/CLKOUT
I/O
I
I
O
Port C, Schmitt Trigger input level
Master Clear, Schmitt Trigger input level
Oscillator Input/external clock input
Oscillator Output/in RC mode, the CLKOUT pin has 1/4
frequency of CLKIN
V
dd
V
ss
Power supply
Ground
Function Description
This specification are subject to be changed without notice. Any latest information
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please preview
P.2
2008/7
Ver. 1.0
MDT10P621N(AB)
Address
12
14
A0~FF
T2PER
SCMSTA
General purpose register
Description
(1) IAR ( Indirect Address Register) : R00
(2) RTCC (Real Time Counter/Counter Register) : R01
(3) PC (Program Counter) : R02,R0A
Write PC --- from PCHLAT
Write PC --- from PCHLAT
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A11
A10~A8
A7~A0
Write PC --- from ALU
LJUMP, LCALL --- from instruction word
RTWI, RET, RTFI --- from STACK
(4) STATUS (Status register) : R03
Bit
0
1
2
3
4
5
Symbol
C
HC
Z
PF
TF
RBS0
Carry bit
Half Carry bit
Zero bit
Power down Flag bit
WDT Timer overflow Flag bit
Register Bank Select bit :
0 : 00H --- 7FH ( Bank0 )
1 : 80H --- FFH ( Bank1 )
6-7
——
General purpose bit
Function
This specification are subject to be changed without notice. Any latest information
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P.4
2008/7
Ver. 1.0
MDT10P621N(AB)
(5) MSR (Memory Bank Select Register) : R04
Memory Bank Select Register :
0 : 00~7F (Bank 0)
1 : 80~FF (Bank1)
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode
(6) PORT A : R05
PA5~PA0, I/O Register
(7) PORT B : R06
PB7~PB0, I/O Register
(8) PORT C : R07
PC7~PC0, I/O Register
(9)PCHLAT : R0A
(10) INTS ( Interrupt Status Register ) : R0B
Bit
0
1
2
3
Symbol
RBIF
INTF
TIF
RBIE
Function
PORT B change interrupt flag. Set when PB <7:4> inputs change
Set when INT interrupt occurs. INT interrupt flag.
Set when TMR0 overflows.
0 : disable PB change interrupt
1 : enable PB change interrupt
4
INTS
0 : disable INT interrupt
1 : enable INT interrupt
5
TIS
0 : disable TMR0 interrupt
1 : enable TMR0 interrupt
6
PEIE
0 : disable all peripheral interrupt
1 : enable all peripheral interrupt
7
GIS
0 : disable global interrupt
1 : enable global interrupt
This specification are subject to be changed without notice. Any latest information
http;//www.mdtic.com.tw
please preview
P.5
2008/7
Ver. 1.0