MDT10P432
1. General Description
This 8-bit Micro-controller with built-in carrier generator uses a fully static CMOS technology to achieve high
speed, small size, low power and high noise immunity.
On chip memory includes 512 words of ROM, and 28 bytes of static RAM.
2. Features
Fully CMOS static design
8-bit data bus
On chip ROM size : 512 words
Internal RAM size : 28 bytes
(24general purpose registers, 4 special registers)
34 single word instructions
14-bit instructions
2-level stacks
Operating voltage : 2.0V ~ 5.0 V
Addressing modes include direct, indirect and relative addressing modes
Power-on Reset
Internal RC 432K, 440K, 455K, 480KHz select in option.
System clock : 455KHz crystal (OSC1 cap 50P; OSC2 cap 50P)
Auto detect external crystal on board .
PA0-7 : 8 input only pins with pull-high resistor and input low wakeup detect circuit.
PB0 : CMOS output.
PB1~7 : Seven open drain output pins.
Built in remote control carrier synthesizer Fosc/8 (56.9K) or Fosc/12 (37.9K) by firmware setting.
Option used PB0 NMOS without BJT.
4096 clocks for external oscillator start up time.
3. Applications
Remote controller
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
1 of 13
2010.7
Ver. 1.4
MDT10P432
4. Pin Assignment
※
P – PDIP, S - PSOP
MDT10P432P11
MDT10P432S11
PA2
PA3
PA6
PA7
VSS
PB0
PB1
PB2
PB3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PA1
PA0
OSC1
OSC2
VDD
PB7
PB6
PB5
PB4
MDT10P432P12
MDT10P432S12
PA2
PA3
PA6
PA7
VSS
PB0
PB1
PB2
PB3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PA5
PA4
PA1
PA0
VDD
PB7
PB6
PB5
PB4
MDT10P432P21
MDT10P432S21
PA5
PA2
PA3
PA6
PA7
VSS
PB0
PB1
PB2
PB3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PA4
PA1
PA0
OSC1
OSC2
VDD
PB7
PB6
PB5
PB4
MDT10P432P31
MDT10P432S31
PA2
PA3
PA6
PA7
VSS
PB0
PB1
PB2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PA1
PA0
OSC1
OSC2
VDD
PB7
PB6
PB5
MDT10P432P34
MDT10P432S34
PA3
PA6
PA7
VSS
PB0
PB1
PB2
PB3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PA2
PA1
PA0
VDD
PB7
PB6
PB5
PB4
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
2 of 13
2010.7
Ver. 1.4
MDT10P432
5. Order Information
Device
MDT10P432P11
MDT10P432P12
MDT10P432P21
MDT10P432P31
ROM
(Words)
0.5K
0.5K
0.5K
0.5K
RAM
(Bytes)
24
24
24
24
I/O
14 (6 input; 8 output)
16 (8 input; 8 output)
16 (8 input; 8 output)
12 (6 input; 6 output)
Package
18-DIP
18-DIP
20-DIP
16-DIP
mil
300
300
300
300
Remark
18 pin ; 6 input (no PA 4~5) ; 8 output
18 pin ; 8 input ; 8 output; (no OSC1&2)
20 pin ; 8 input ; 8 output
16 pin ; 6 input (no PA 4&5) ; 6 output
(no PB 3&4)
16 pin ; 6 input (no PA 4~5) ; 8 output;
(no OSC1&2)
18 pin ; 6 input (no PA 4~5) ; 8 output
18 pin ; 8 input ; 8 output; (no OSC1&2)
20 pin ; 8 input ; 8 output
16 pin ; 6 input (no PA 4&5) ; 6 output
(no PB 3&4)
16 pin ; 6 input (no PA 4~5) ; 8 output;
(no OSC1&2)
MDT10P432P34
MDT10P432S11
MDT10P432S12
MDT10P432S21
MDT10P432S31
0.5K
0.5K
0.5K
0.5K
0.5K
24
24
24
24
24
14 (6 input; 8 output)
14 (6 input; 8 output)
16 (8 input; 8 output)
16 (8 input; 8 output)
12 (6 input; 6 output)
16-DIP
18-SOP
18-SOP
20-SOP
16-SOP
300
300
300
300
150
MDT10P432S34
0.5K
24
14 (6 input; 8 output)
16-SOP
150
6. Block Diagram
Stack Tw o
Levels
9 bits
RO M
512×14
9 bits
14 bits
RA M
24×8
Port A
Port
PA 0~PA 7
8 bits
Program
C ounters
Instruction
R egister
Special R egister
Port PB0
D 0~D 7
Port B
Instruction
D ecoder
D ata
8bit
Port
PB1~PB7
External X T
Internal R C
C ontrol C ircuit
Pow er on R eset
Pow er D ow n R eset
W orking R egister
A LU
Status R egister
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
3 of 13
2010.7
Ver. 1.4
MDT10P432
7. Pin Function Description
Pin Name
PA0~PA7
I/O
I
Function Description
Port A, TTL input level. Built in 50K ohm pull-high resistor. In sleep
mode, a high-to-low change on any pin will cause chip reset.
PB0
O
CMOS output pin.
Enable NMOS sink 250mA by option (replace BJT)
PB1~PB7
OSC1
OSC2
Vdd
Vss
O
I
O
Port B open drain output pins, 50K ohm pull-high resistor.
Crystal oscillation input pin
Crystal oscillation output pin
Power supply
Ground
8. Memory Map
8.1 Program memory :
000H
Program memory
1FEH
1FFH
8.2
Register Map
Address
00
01
02
03
04
05
06
07
08~1F
Description
Indirect Addressing Register
Unimplemented
PC
STATUS
MSR
Port A (Input Only)
Port B output register
Unimplemented
Internal RAM, General Purpose Register
Reset Vector
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
4 of 13
2010.7
Ver. 1.4
MDT10P432
(1) IAR ( Indirect Address Register) : R0
(2) PC (Program Counter) : R2
Write PC, CALL --- always 0
LJUMP, JUMP, LCALL --- from instruction word
RTIW, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5
LJUMP, LCALL --- from instruction word
RTIW, RET --- from STACK
Write PC --- from ALU
LJUMP, JUMP, LCALL, CALL --- from instruction word
RTIW, RET --- from STACK
(3) STATUS (Status register) : R3
Bit
0
1
2
3
4
Symbol
C
HC
Z
/PF
/LPT
Carry bit
Half Carry bit
Zero bit
Power loss Flag bit
Low power detect
=0 : Vdd is lower than 2.1 ~ 2.3V
=1 : Vdd is higher than 2.1 ~ 2.3V
5
7-6
——
——
General purpose bit
Carrier frequency control bits
=00 No carrier (default)
=01 Fosc/8, 1/2 duty
=10 Fosc/12, 1/2 duty
=11 Fosc/12, 1/3 duty (1/3 – Hi ; 2/3 - Low)
(4) MSR (Memory Select Register) : R4
(5) PORT A : R5
Bit 7-0 : Port A data input
(6) PORT B : R6
Bit 7-1 : PB7-PB1 output register (open drain output)
Bit 0
: PB0 output register (CMOS output)
Function
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
5 of 13
2010.7
Ver. 1.4
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