VSC8221
Data Sheet
Single-Port 10/100/1000BASE-T PHY with 1.25 Gbps SerDes for SFPs/GBICs
1 G
ENERAL
D
ESCRIPTION
Ideally suited for Ethernet Switches with SGMII/SerDes MAC
Interfaces, Media Converter applications, and SFP/GBIC
modules, the industry-leading, low-power VSC8221 from
Vitesse integrates a high-performance 1.25Gbps SerDes and
a triple speed (10/100/1000BASE-T) transceiver, providing
unmatched tolerance to noise and cable plant imperfections.
Consuming approximately 700mW and eliminating the need
for external power supply regulators, the device requires only
a single 3.3V power supply. To further minimize system
complexity and cost, the VSC8221's twisted pair interface
features fully integrated line terminations, exceptionally low
EMI, and robust Cable Sourced ESD (CESD) performance.
The VSC8221 offers direct connectivity to SGMII or SerDes
interfaces. In 1000BASE-X SerDes mode, the VSC8221 may
be used to connect a MAC to copper media (MAC to Cat-5)
or to 100BASE-FX (over its copper media interface). In
SGMII mode, the VSC8221 provides a fully compliant, 4-pin
or 6-pin interface to MACs. The 1000BASE-X SerDes and
SGMII interfaces offer either automatic or user-controlled
auto-negotiation priority resolution between the 1000BASE-X
and 1000BASE-T auto-negotiation processes. A single chip
copper-to-optics Media Converter can be easily implemented
by simultaneous use of the SerDes and Cat-5 media
interfaces.
To minimize power consumption, the VSC8221 offers several
programmable power management modes. The device also
supports the comprehensive VeriPHY
®
Cable Diagnostics
feature from Vitesse, offering the system manufacturer and IT
administrator a complete suite of cable plant diagnostics to
simplify the manufacture, installation, and management of
Gigabit-over-copper networks.
2 F
EATURES AND
B
ENEFITS
Features
•
Very low power consumption
Benefits
•
•
Reduces power supply costs
Fully compliant with SFP MSA’s power dissipation
specification of less than 1W maximum per module
Eliminates external regulators, reducing system costs
Connects to serial MACs or optical modules
Supports triple-speed copper SFP/GBIC modules
May allow use of SimpliPHY’d Magnetics with up to 50%
cost savings versus competition
Saves over 12 external components per port and
reduces PCB area and cost by 50%
Can enable a superior, FCC Class B capable EMI
solution for copper SFPs
Ensures trouble-free deployment in real world Ethernet
networks
Reduces power consumption and system cost
Suitable for Gigabit switch ports, SFPs/GBICs, and
media converters
•
•
•
Single 3.3V power supply with on-chip regulator
SGMII & SerDes Interfaces
Patented line driver with integrated line side termination
resistors
•
•
•
•
•
•
•
•
•
Over 150m of Cat-5 reach with the industry’s highest
noise tolerance
Several flexible power management modes
Small footprint 9mm x 9mm, 100-TFBGA package
•
•
•
3 A
PPLICATIONS
•
Triple-speed SFP/GBIC modules
•
Media converters
VMDS-10106 Revision 4.1 ©
VITESSE SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896
December 2006
Internet: www.vitesse.com
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VSC8221
Data Sheet
6 R
ELEVANT
S
PECIFICATIONS
& D
OCUMENTATION
The VSC8221 conforms to the following specifications. Please refer to these documents for additional information.
Table 1. Specifications and Documentation
Specification - Revision
Description
Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and
Physical Layer Specifications. IEEE 802.3-2002 consolidates and supersedes the following
specifications:
802.3ab (1000BASE-T), 802.3z (1000BASE-X), 802.3u (Fast Ethernet), with references to
ANSI X3T12 TP-PMD standard (ANSI
X3.263 TP-PMD)
Test Access Port and Boundary Scan Architecture
1
.
Includes IEEE Standard 1149.1a-1993 and IEEE Standard 1149.1b-1994
2.5V±0.2V (Normal Range), and 1.8V to 2.7V (Wide Range) Power Supply Voltage and
Interface Standard for Nonterminated Digital Integrated Circuits
Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)
Revision of JESD22-A114-A
Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)
Revision of EIA/JESD22-A115
IC Latch-Up Test Standard
Miltary Test Method Standard for Microcircuits
Cisco SGMII specification
IP Backplane for CompactPCI
IP Backplane specification for CompactPCI v3.0
Cisco Systems InLine Power Detection:
http://www.cisco.com/en/US/products/hw/phones/ps379/
products_tech_note09186a00801189b5.shtml
IEEE 802.3-2002
IEEE 1149.1-1990
JEDEC EIA/JESD8-5
JEDEC JESD22-A114-B
JEDEC JESD22-A115-A
JEDEC EIA/JESD78
MIL-STD-883E
Cisco SGMII v1.7
PICMG 2.16
Advanced TCA™ Base
PICMG 3.0
Cisco InLine Power Detection
Algorithm
Small Form-factor Pluggable
Specification for pluggable fiber optic transceivers. Describes module data access protocol
(SFP) Transceiver MultiSource
and interface
Agreement
1
Often referred to as the “JTAG” test standard.
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VMDS-10106 Revision 4.1
December 2006
VSC8221
Data Sheet
7 D
ATA
S
HEET
C
ONVENTIONS
Conventions used throughout this data sheet are specified in the following table.
Table 2. Data Sheet Conventions
Convention
Register
number
Extended
Page Regis-
ter Number
1
Signal name
(active high)
Signal name
(active low)
Signal bus
name
1
2
Syntax
RegisterNumber.Bit
or
RegisterNumber.BitRange
RegisterNumberE.Bit
or
RegiesterNumberE.BitRange
SIGNALNAME
2
SIGNALNAME
2
BUSNAME[MSB:LSB]
2
Examples
23.10
23.12:10
23E.10
23E.12:10
PLLMODE
RESET
RXD[4:2]
Description
Register 23 (address 17h), bit 10
Register 23 (address 17h), bits 12, 11, and 10
Extended Register 23 (address 17h), bit 10
Extended Register 23 (address 17h), bits 12, 11, and 10
Signal name for PLLMODE
Active low reset signal
Receive Data bus, bits 4, 3, and 2
For more information about MII Extended Page Registers, refer to
Section 22: "PHY Register Set Conventions"
on page 63.
All signal names are in all CAPITAL LETTERS.
5 of 138
VMDS-10106 Revision 4.1
December 2006
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