Crystal oscillator
MULTI-OUTPUT CRYSTAL OSCILLATOR
MG - 5100SA
series
Product number (Please contact us)
Q33M21SA1xxxxx00
•Frequency
range
:
76.9 kHz to 100 MHz
•Operating
voltage
:
3.3 V or 5.0 V
•Built-in
crystal
:
AT crystal unit
•Thickness
:
3.2 mm Typ.
•Lead(Pb)-free
:
Complies with EU RoHS directive
•Available
output in 8 frequencies by selecting pin
for CPU CLK.
Actual size
■
Specifications (characteristics)
Item
Output frequency range
Power source Max. supply voltage
voltage
Operating voltage
Temperature
Storage temperature
range
Operating temperature
Frequency stability
Current consumption
Duty
High output voltage
Low output voltage
Output condition
Output enable /
disenable input voltage
Output rise time
Output fall time
Jitter
Skew
Oscillation start up time
Aging
Symbol
f
0
V
DD
-GND
V
DD
T
STG
T
OPR
∆f/f
0
I
OP
tw/t
V
OH
V
OL
C
L
V
IH
V
IL
Specifications
V
DD
=5.0V
V
DD
=3.3V
76.9 kHz to 100 MHz
76.9 kHz to 80 MHz
-0.3 V to +7.0 V
5.0 V ±0.5 V
3.3 V ±0.3 V
-55
°C
to +100
°C
-20
°C
to +70
°C
±100 × 10
-6
100 mA Max.
65 mA Max.
40 % to 60 %
V
DD
-0.4 V Min.
0.4 V Max.
15 pF Max.
80 % V
DD
Min.
20 % V
DD
Max.
5 ns Max.
4 ns Max.
450 ps Max.
500 ps Max.
500 ps Max
70 ms Max.
±5 × 10
-6
/ year Max.
Remarks
Please contact us for inquiries about the available frequency.
Stored as bare product after unpacking
No load, Max. frequency
50 % V
DD
, CL=15 pF
I
OH
=-4 mA
I
OL
=4 mA
Max. frequency and Max. operating voltage
20 %→80 % V
DD
80 %→20 % V
DD
Cycle to Cycle jitter
Peak to Peak jitter
Please contact us for inquiries about details.
Time at minimum operating voltage to be 0s.
T
a
=+25
°C,V
DD
=5.0 V/ 3.3 V, First year
t
R
t
F
t
j
t
skw
t
OSC
fa
■
Block diagram
TIN
OSC.
PLL 2
PLL 3
XBUF
PLL 1
OUTPUT
MULTIPLEXER
AND
DIVIDERS
CPUCLK
CLKA
CLKB
CLKC
CLKD
Pin terminal
XBUF
CPUCLK
CLKA
CLKB
CLKC
CLKD
S0
S1
S2
TIN
OE
••••• Output pin of internal X’tal
••••• Output pin
••••• Output pin
••••• Output pin
••••• Output pin
••••• Output pin
••••• CPUCLK Output frequency select pin 0
••••• CPUCLK Output frequency select pin 1
••••• CPUCLK Output frequency select pin 2
••••• Test pin.Do not connect them to any terminals.
••••• Output control ("H"? Output ,"L"? weak pull - down)
S2
S1
S0
OE
ROM AND LOGIC
■
External dimensions
10.1
±
0.2
#14
#8
(Unit:mm)
■
Recommended soldering pattern
(Unit:mm)
7.4
±
0.2
M5100 AB
5.0
E 935 6A
#1
#7
#1
0.05
Min.
0.35
3.2
±
0.1
#7
0.15
0.7
0° - 10°
1.27
1.27
1.2
0.6
7.62
Metal may be exposed on the top or bottom of this product.
T his won't affect any quality, reliability or electrical spec.
2.0
5.4
No.
1
2
3
4
5
6
7
Pin terminal
S1
S0
CLKA
CLKB
CPUCLK
CLKD
XBUF
No.
14
13
12
11
10
9
8
Pin terminal
V
DD1
V
DD2
S2
OE
CLKC
GND
TIN
#14
#8
2.0
52
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