SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
D
D
D
D
2-V to 6-V V
CC
Operation
Inputs Accept Voltages to 6 V
Max t
pd
of 8.5 ns at 5 V
3-State Outputs Drive Bus Lines Directly
SN54AC574 . . . J OR W PACKAGE
SN74AC574 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the
′AC574
devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal
logic state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in a bus-organized system without need
for interface or pullup components.
OE does not affect internal operations of the
flip-flop. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
ORDERING INFORMATION
T
A
PDIP − N
SOIC − DW
−40°C to 85°C
40 C 85 C
SOP − NS
SSOP − DB
TSSOP − PW
CDIP − J
−55°C to 125 C
55 C 125°C
†
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
SN54AC574 . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
V
CC
3D
4D
5D
6D
7D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Q
2Q
3Q
4Q
5Q
6Q
PACKAGE
†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74AC574N
SN74AC574DW
SN74AC574DWR
SN74AC574NSR
SN74AC574DBR
SN74AC574PW
SN74AC574PWR
SNJ54AC574J
SNJ54AC574W
SNJ54AC574FK
CFP − W
LCCC − FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
8D
GND
CLK
8Q
7Q
TOP-SIDE
MARKING
SN74AC574N
AC574
AC574
AC574
AC574
SNJ54AC574J
SNJ54AC574W
SNJ54AC574FK
1
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
↑
↑
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q
0
Z
logic diagram (positive logic)
OE
CLK
1
11
C1
1D
2
1D
19
1Q
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Package thermal impedance,
θ
JA
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
†
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
SN54AC574
MIN
V
CC
V
IH
Supply voltage
V
CC
= 3 V
High level
High-level input voltage
V
CC
= 4.5 V
V
CC
= 5.5 V
V
CC
= 3 V
V
IL
V
I
V
O
I
OH
Low level
Low-level input voltage
Input voltage
Output voltage
V
CC
= 3 V
High-level output current
High level
V
CC
= 4.5 V
V
CC
= 5.5 V
V
CC
= 3 V
I
OL
Δt/Δv
T
A
Low level
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−55
V
CC
= 4.5 V
V
CC
= 5.5 V
V
CC
= 4.5V
V
CC
= 5.5 V
0
0
2
2.1
3.15
3.85
0.9
1.35
1.65
V
CC
V
CC
−12
−24
−24
12
24
24
8
125
−40
0
0
MAX
6
SN74AC574
MIN
2
2.1
3.15
3.85
0.9
1.35
1.65
V
CC
V
CC
−12
−24
−24
12
24
24
8
85
ns/V
°C
mA
mA
V
V
V
V
MAX
6
UNIT
V
NOTE 3: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
3V
I
OH
= −50
μA
50
V
OH
I
OH
= −12 mA
I
OH
= −24 mA
24
4.5 V
5.5 V
3V
4.5 V
5.5 V
3V
I
OL
= 50
μA
V
OL
I
OL
= 12 mA
I
OL
= 24 mA
I
I
I
OZ
I
CC
C
i
V
I
= V
CC
or GND
V
O
= V
CC
or GND
V
I
= V
CC
or GND,
V
I
= V
CC
or GND
I
O
= 0
4.5 V
5.5 V
3V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5V
4.5
T
A
= 25°C
MIN
2.9
4.4
5.4
2.56
3.94
4.94
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
±0.5
4
TYP
MAX
SN54AC574
MIN
2.9
4.4
5.4
2.4
3.7
4.7
0.1
0.1
0.1
0.5
0.5
0.5
±1
±5
80
MAX
SN74AC574
MIN
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1
±2.5
40
μA
μA
μA
pF
V
V
MAX
UNIT
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
±
0.3 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
MIN
f
clock
t
w
t
su
t
h
Clock frequency
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
6
2.5
1.5
MAX
75
7.5
6.5
2.5
SN54AC574
MIN
MAX
55
7
3
1.5
SN74AC574
MIN
MAX
60
UNIT
MHz
ns
ns
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
±
0.5 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
MIN
f
clock
t
w
t
su
t
h
Clock frequency
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
4
1.5
1.5
MAX
95
5
3.5
2.5
SN54AC574
MIN
MAX
85
5
2
1.5
SN74AC574
MIN
MAX
85
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
CLK
OE
OE
Q
Q
Q
TO
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
MIN
75
3.5
3.5
2.5
3
3.5
2
TYP
112
8.5
7.5
7
6.5
7.5
5.5
13.5
12
11
10.5
12
9
MAX
SN54AC574
MIN
55
1
1
1
1
1
1
16.5
15
13
12.5
14
10.5
MAX
SN74AC574
MIN
60
3.5
3.5
2.5
3
2.5
1.5
15
13.5
12
11.5
13
10
ns
ns
ns
MAX
UNIT
MHz
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
CLK
OE
OE
Q
Q
Q
TO
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
MIN
95
2
2
2
2
2
1
TYP
153
6
5.5
5
5
6
4.5
9.5
8.5
8.5
8
9.5
7.5
MAX
SN54AC574
MIN
85
1.5
1.5
1.5
1.5
1.5
1.5
11.5
10.5
9.5
9.5
11.5
9
MAX
SN74AC574
MIN
85
2
2
2
1.5
1.5
1
11
9.5
9
9
10.5
8.5
ns
ns
ns
MAX
UNIT
MHz
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
C
pd
Power dissipation capacitance
TEST CONDITIONS
C
L
= 50 pF,
f = 1 MHz
TYP
40
UNIT
pF
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2
×
V
CC
From Output
Under Test
C
L
= 50 pF
(see Note A)
500
Ω
S1
Open
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
2
×
V
CC
Open
500
Ω
LOAD CIRCUIT
V
CC
Timing Input
t
w
3V
Input 50% V
CC
50% V
CC
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Data Input
t
su
50% V
CC
50% V
CC
0V
t
h
V
CC
50% V
CC
0V
V
CC
Input
50% V
CC
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
50% V
CC
50% V
CC
50% V
CC
0V
t
PHL
V
OH
50% V
CC
V
OL
t
PLH
V
OH
50% V
CC
V
OL
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
t
PZL
Output
Waveform 1
S1 at 2
×
V
CC
(see Note B)
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
CC
50% V
CC
50% V
CC
0V
t
PLZ
≈V
CC
50%V
CC
V
OL
+ 0.3 V
t
PHZ
50% V
CC
V
OH
− 0.3 V
V
OH
≈0
V
VOLTAGE WAVEFORMS
V
OL
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, Z
O
= 50
Ω,
t
r
≤
2.5 ns, t
f
≤
2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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