May 2003
Advance Information
®
AS7C331MPFS18A
1M x 18 pipelined burst synchronous SRAM
Features
•
•
•
•
•
•
•
•
Organization: 1,048,576 x18 bits
Fast clock speeds to 200MHz in LVTTL/LVCMOS
Fast clock to data access: 3/3.4/3.8 ns
Fast OE access time: 3/3.4/3.8 ns
Fully synchronous register-to-register operation
Single register flow-through mode
Single-cycle deselect
Asynchronous output enable control
•
•
•
•
•
•
Available 100-pin TQFP and 165-ball BGA packages
Byte write enables
Multiple chip enables for easy expansion
3.3 V core power supply
2.5 V or 3.3V I/O operation with separate V
DDQ
NTD™ pipelined architecture available (AS7C331MNTD18A,
AS7C33512NTD32A/ AS7C33512NTD36A)
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[19:0]
CLK
CS
CLR
Burst logic
Q
20
D
CS
CLK
20
18 20
Address
register
1M
[
18
Memory
array
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
18
Byte Write
registers
Byte Write
registers
CLK
D
CLK
D
DQa
Q
2
OE
Enable
Q
register
CE
CLK
ZZ
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
FT DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
5
200
3.0
370
130
70
-166
6
166
3.4
340
120
70
-133
7.5
133
3.8
320
110
70
Units
ns
MHz
ns
mA
mA
mA
5/28/03, v. 052003 Advance Info
Alliance Semiconductor
1 of 21
Copyright © Alliance Semiconductor. All rights reserved.
AS7C331MPFS18A
®
Pin and ball designations
Pin configuration for 100-pin TQFP
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQPb
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 × 20 mm
1M x 18
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQa
DQa
DQa
V
SSQ
V
DDQ
DQ
a
DQ
a
V
SS
NC
VDD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
Ball assignments for 165-ball BGA
$
%
&
'
(
)
*
+
-
.
/
0
1
3
5
NC
NC
NC
NC
NC
NC
NC
FT
DQb
DQb
DQb
DQb
DQPb
NC
LBO
A
A
NC
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
NC
NC
NC
CE0
CE1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
NC
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1
1
A0
1
BWE
GWE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
ADSC
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
5/28/03, v. 052003 Advance Info
Alliance Semiconductor
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AS7C331MPFS18A
®
Functional description
The AS7C331MPFS18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as
1,048,576 words X 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology.
Fast cycle times of 5/6/7.5 ns with clock access times (t
CD
) of 3/3.4/3.8 ns enable 200, 166, and 133 MHz bus frequencies. Three chip
enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or
the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK is carried to the data-out registers and driven on
the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes
are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count
sequence. With LBO driven low, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all
18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled low, regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally
to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
•
Master chip enable
CE0 blocks ADSP, but not ADSC.
The AS7C331MPFS18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin TQFP and 165-ball BGA.
TQFP and BGA capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
Address and control pins
I/O pins
Test conditions
V
IN
= 0V
V
IN
= V
OUT
Max
5
7
Unit
pF
pF
5/28/03, v. 052003 Advance Info
Alliance Semiconductor
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AS7C331MPFS18A
®
Signal descriptions
Signal
CLK
A0–A17
DQ[a,b]
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b]
OE
LBO
TDO
TDI
TMS
TCK
FT
ZZ
I/O
I
I
I/O
I
I
I
I
I
I
I
I
I
I
O
I
I
O
I
I
Properties
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
SYNC
SYNC
SYNC
SYNC
STATIC
ASYNC
Description
Clock. All inputs except OE, FT, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.
Synchronous chip enables. Active high and active low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted low to load a new bus address or to enter standby
mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and
BW[a,b] control write enable.
Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is
low. If any of BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If
all BW[AB] are inactive, the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention.
This signal is internally pulled high.
18
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK
(BGA only).
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Flow-through mode.When low, enables single register flow-through mode. Connect to
V
DD
if unused or for pipelined operation.
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Write enable truth table (per byte)
Function
Write all bytes (a, b)
Write byte a
Write byte b
Read
GWE
L
H
H
H
H
H
BWE
X
L
L
L
H
L
BWa
X
L
L
H
X
H
BWb
X
L
H
L
X
H
.H\
X = don’t care; L = low; H = high; B
WE, BWn
= internal write signal
5/28/03, v. 052003 Advance Info
Alliance Semiconductor
4 of 21
AS7C331MPFS18A
®
Synchronous truth table
CE0
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
CE1
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
CE2
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
ADSP
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
ADSC
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
BWn
1
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
T
T
T
T
T
OE
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
Address accessed
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
DQ
Hi
−
Z
Hi
−
Z
Hi
−
Z
Hi
−
Z
Hi
−
Z
Hi
−
Z
2
Hi
−
Z
Hi
−
Z
2
Hi
−
Z
Q
Hi
−
Z
Q
Hi
−
Z
Q
Hi
−
Z
Q
Hi
−
Z
D
3
D
D
D
D
1
See “Write enable truth table” on page 4 for more information.
2 Q in flow-through mode.
3
For a write operation following a read operation,
OE
must be high before the input data set up time and must be held high throughout the input hold time
Key: X = don’t care, L = low, H = high
TQFP and BGA thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1
This parameter is sampled.
1 layer
4 layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°
C/W
°
C/W
°
C/W
Conditions
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
5/28/03, v. 052003 Advance Info
Alliance Semiconductor
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