Product Specification
PE64907
Product Description
PE64907 is a DuNE™ technology-enhanced Digitally
Tunable Capacitor (DTC) based on Peregrine’s UltraCMOS
®
technology. This highly versatile product supports a wide
variety of tuning circuit topologies with emphasis on
impedance matching and aperture tuning applications.
PE64907 offers high RF power handling and ruggedness
while meeting challenging harmonic and linearity
requirements enabled by Peregrine’s HaRP™ technology.
The device is controlled through the widely supported 3-wire
(SPI compatible) interface. All decoding and biasing is
integrated on-chip and no external bypassing or filtering
components are required.
DuNE™ devices feature ease of use while delivering
superior RF performance in the form of tuning accuracy,
monotonicity, tuning ratio, power handling, size, and quality
factor. With built-in bias voltage generation and ESD
protection, DTC products provide a monolithically integrated
tuning solution for demanding RF applications.
UltraCMOS
®
Digitally Tunable Capacitor
(DTC)
100-3000 MHz
Features
3-wire (SPI) compatible serial interface
with built-in bias voltage generation and
ESD protection
DuNE™ technology enhanced
5-bit 32-state Digitally Tunable Capacitor
Shunt configuration C = 0.85 pF to 2.4 pF
(2.82:1 tuning ratio) in discrete 50 fF
steps
High RF power handling (30 V
pk
RF) and
linearity
Wide power supply range (2.3V to 4.8V)
and low current consumption
(typ. 140
μA
at 2.75V)
High ESD tolerance of 2kV HBM on all
pins
Applications include:
Tunable antennas
Tunable matching networks
Tunable filter networks
Phase shifters
Figure 1. Functional Diagram
Figure 2. Package Type
10-lead 2 x 2 x 0.55 mm QFN
RF+
ESD
ESD
RF-
Serial
Interface
CMOS Control
Driver and ESD
DOC-02169
Document No. DOC-30214-2
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Page 1 of 10
PE64907
Product Specification
Table 1. Electrical Specifications @ 25°C, V
DD
= 2.75V (In shunt configuration, RF- connected to GND)
Parameter
Operating frequency
Minimum capacitance
(C
min
)
Maximum capacitance
(C
max
)
Tuning ratio
Step size
Quality factor at C
min1
Quality Factor at C
max1
Self resonant frequency
Harmonics
2
IMD3
Third order intercept point
(IP3)
Switching time
3,4
Start-up time
3
Wake-up time
3,4
State 00000, 100 MHz
State 11111, 100 MHz
C
max
/C
min
, 100 MHz
5 bits (32 states), 100 MHz
698 - 960 MHz, with L
S
removed
1710 - 2170 MHz, with L
S
removed
698 - 960 MHz, with L
S
removed
1710 - 2170 MHz, with L
S
removed
State 00000
State 11111
2fo, 3fo: 698 - 915 MHz; P
IN
+34 dBm, 50Ω
2fo, 3fo: 1710 - 1910 MHz; P
IN
+32 dBm, 50Ω
Bands I,II,V/VIII, +20 dBm CW @ TX freq,
-15 dBm CW @ 2Tx-Rx freq, 50Ω
Shunt configuration derived from IMD3 spec
IP3 = (2P
TX
+ P
block
- IMD3) / 2
State change to 10/90% delta capacitance between any two states
Time from V
DD
within specification to all performances within specification
State change from Standby mode to RF state to all performances within specification
65
12
70
70
Condition
Min
100
0.77
2.16
0.85
2.40
2.82:1
0.050
41
37
34
16
8.3
3.5
-36
-36
-105
GHz
dBm
dBm
dBm
dBm
µs
µs
µs
pF
Typ
Max
3000
0.94
2.64
Unit
MHz
pF
pF
Notes: 1. Q for a shunt DTC based on a series RLC equivalent circuit
Q = X
C
/ R = (X - X
L
) / R, where X = X
L
+ X
C
, X
L
= 2*pi*f*L, X
C
= -1 / (2*pi*f*C), which is equal to removing the effect of parasitic inductance L
S
2. In shunt between 50Ω ports. Pulsed RF input with 4620 µS period, 50% duty cycle, measured per 3GPP TS 45.005
3. DC path to ground at RF– must be provided to achieve specified performance
4. State change activated on falling edge of SEN following data word
©2013 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 10
Document No. DOC-30214-2
│
UltraCMOS
®
RFIC Solutions
PE64907
Product Specification
Figure 3. Pin Configuration (Top View)
Table 3. Operating Ranges
Parameter
Supply voltage
Supply current (V
DD
= 2.75V)
Standby current (V
DD
= 2.75V)
Control voltage high
Control voltage low
RF input power (50Ω)
1
698 - 915 MHz
1710 - 1910 MHz
Peak operating RF voltage
2
V
P
to V
M
V
P
to RFGND
Operating temperature range
T
OP
T
ST
-40
-65
+25
+25
Symbol
V
DD
I
DD
I
DD
V
IH
V
IL
1.2
0
Min
2.30
Typ
2.75
140
25
1.8
0
3.1
0.57
+34
+32
30
30
+85
+150
Max
4.80
200
Unit
V
µA
µA
V
V
dBm
dBm
Vpk
Vpk
°C
°C
Table 2. Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
Pad
Pin Name
RF-
RF-
GND
V
DD
SCL
SEN
SDA
RF+
RF+
GND
GND
Description
Negative RF port
1
Negative RF port
1
Ground
2
Power supply pin
Serial interface clock input
Serial interface latch enable input
Serial interface data input
Positive RF port
1
Positive RF port
Ground
2
1
Storage temperature range
Notes:
1. Maximum power available from 50Ω source. Pulsed RF input with
4620 µS period, 50% duty cycle, measured per 3GPP TS 45.005
measured in shunt between 50Ω ports, RF- connected to GND
2. Node voltages defined per Equivalent Circuit Model Schematic
(Figure
13).
When DTC is used as a part of reactive network,
impedance transformation may cause the internal RF voltages (V
P
, V
M
)
to exceed peak operating RF voltage even with specified RF input
power levels. For operation above about +20 dBm (100 mW), the
complete RF circuit must be simulated using actual input power and
load conditions, and internal node voltages (V
P
, V
M
in
Figure 13)
monitored to not exceed 30 V
pk
Table 4. Absolute Maximum Ratings
Parameter/Condition
ESD Voltage HBM
1
Symbol
V
ESD
Min
Max
2000
Unit
V
Note 1: Human Body Model (MIL-STD-883 Method 3015.7)
Exposed pad: ground for proper operation
2
Notes: 1. For optimal performance, recommend typing Pins 1-2 and Pins 8-9
together on PCB
2. For optimal performance, recommend tying Pins 3, 10, and
exposed ground pad together on PCB
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE64907 in the 10-lead 2 x 2 x 0.55 mm QFN
package is MSL1.
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted
to the limits in the Operating Ranges table.
Operation between operating range maximum and
absolute maximum for extended periods may
reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
Document No. DOC-30214-2
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Page 3 of 10
PE64907
Product Specification
Performance Plots @ 25°C and 2.75V unless otherwise specified
Figure 4. Measured Shunt C (@ 100 MHz) vs State
3
2.5
2
1.5
1
0.5
0
Figure 5. Measured Shunt S
11
(major states)
Capacitance (pF)
C0
C1
C2
C4
C8
C15
C31
0
5
10
15
State
20
25
30
Frequency(800 - 900 MHz)
Figure 6. Measured Step Size vs State (frequency)
200
180
160
140
Step size (fF)
120
100
80
60
40
20
0
5
10
15
State
20
25
30
100 MHz
1000 MHz
2000 MHz
Figure 7. Measured Shunt C vs Frequency
(major states)
5
4.5
4
Capacitance (pF)
3.5
3
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
Frequency(GHz)
2.5
C0
C1
C2
C4
C8
C15
C31
Figure 8. Measured Shunt Q vs Frequency
(major states)
q y ( j
)
120
100
80
60
40
20
0
C0
C1
C2
C4
C8
C15
C31
Figure 9. Measured Shunt Q vs State
60
50
40
30
20
10
698 MHz
960 MHz
1710 MHz
2170 MHz
State
Q
Q
0
0.5
1
1.5
2
Frequency(GHz)
2.5
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Document No. DOC-30214-2
│
UltraCMOS
®
RFIC Solutions
©2013 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 10
PE64907
Product Specification
Serial Interface Operation and Sharing
The PE64907 is controlled by a three wire SPI-
compatible interface with enable active high. As
shown in
Figure 10,
the serial master initiates the
start of a telegram by driving the SEN (Serial
Enable) line high. Each bit of the 8-bit telegram
(MSB first in) is clocked in on the rising edge of
SCL (Serial Clock), as shown in
Table 5
and
Figure 10.
Transitions on SDA (Serial Data) are
allowed on the falling edge of SCL. The DTC
activates the data on the falling edge of SEN. The
DTC does not count how many bits are clocked and
only maintains the last 8 bits it received.
Figure 10. Serial Interface Timing Diagram
t
EOW
t
ESU
t
DSU
t
DHD
t
R
t
F
t
SCL
t
SCLH
t
SCLL
t
EHD
More than 1 DTC can be controlled by one interface
by utilizing a dedicated enable (SEN) line for each
DTC. SDA, SCL, and V
DD
lines may be shared as
shown in
Figure 11.
Dedicated SEN lines act as a
chip select such that each DTC will only respond to
serial transactions intended for them. This makes
each DTC change states sequentially as they are
programmed.
Alternatively, a dedicated SDA line with common
SEN can be used. This allows all DTCs to change
states simultaneously, but requires all DTCs to be
programmed even if the state is not changed.
SEN
SCL
SDA
b0
b7
b6
b5
b4
b3
b2
b1
b0
DTC Data
D
m-2
<7:0>
D
m-1
<7:0>
D
m
<7:0>
Table 5. 8-Bit Serial Programming Register Map
b7
0
1
Figure 11. Recommended Bus Sharing
RF+
V
DD
V
DD
SDA
SCL
SEN
GND
RF-
SDA
SCL
SEN1
SEN2
b6
0
1
b5
STB
2
b4
d4
b3
d3
b2
d2
b1
d1
b0
d0
DTC 1
MSB (first in)
LSB (last in)
Notes: 1. These bits are reserved and must be written to 0 for proper operation
2. The DTC is active when low (set to 0) and in low-current stand-by
mode when high (set to 1)
Table 6. Serial Interface Timing Characteristics
V
DD
= 2.75V, -40 °C < T
A
< +85 °C, unless otherwise specified
Symbol
t
SCL
t
SCLL
t
SCLH
t
R
t
F
t
ESU
t
EHD
t
DSU
t
DHD
t
EOW
Parameter
Serial Clock Period
SCL Low Time
SCL High Time
SCL, SDA, SEN Rise Time
SCL, SDA, SEN Fall Time
SEN rising edge to SCL rising edge
SCL rising edge to SEN falling edge
SDA valid to SCL rising edge
SDA valid after SCL rising edge
SEN falling edge to SEN rising edge
19.2
19.2
13.2
13.2
38.4
Min
38.4
13.2
13.2
6.5
6.5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RF+
V
DD
SDA
SCL
SEN
GND
RF-
DTC 2
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