19-3758; Rev 0; 8/05
IT
TION K
VALUA
E
BLE
AVAILA
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
General Description
Features
o
80Msps Minimum Sampling Rate
o
-82dBFS Noise Floor
o
Excellent Dynamic Performance
80dB/79.2dB SNR at f
IN
= 10MHz/70MHz
and -2dBFS
96dBc/102dBc Single-Tone SFDR1/
SFDR2 at f
IN
= 10MHz
84.3dBc/100dBc Single-Tone SFDR1/
SFDR2 at f
IN
= 70MHz
o
Less than 0.1ps Sampling Jitter
o
1.1W Power Dissipation
o
2.56V
P-P
Fully Differential Analog Input Voltage
Range
o
CMOS-Compatible Two’s-Complement Data
Output
o
Separate Data Valid Clock and Over-Range
Outputs
o
Flexible Input Clock Buffer
o
3.3V Analog Power Supply; 1.8V Digital Output
Supply
o
Small 8mm x 8mm x 0.8mm 56-Pin Thin QFN
Package
o
EV Kit Available for MAX19586
(Order MAX19586EVKIT)
MAX19586
The MAX19586 is a 3.3V, high-speed, high-perfor-
mance analog-to-digital converter (ADC) featuring a
fully differential wideband track-and-hold (T/H) and a
16-bit converter core. The MAX19586 is optimized for
multichannel, multimode receivers, which require the
ADC to meet very stringent dynamic performance
requirements. With a -82dBFS noise floor, the
MAX19586 allows for the design of receivers with supe-
rior sensitivity requirements.
At 80Msps, the MAX19586 achieves a 79.2dB signal-to-
noise ratio (SNR) and an 84.3dBc/100dBc single-tone
spurious-free dynamic range (SFDR) performance
(SFDR1/SFDR2) at f
IN
= 70MHz. The MAX19586 is not
only optimized for excellent dynamic performance in
the 2nd Nyquist region, but also for high-IF input fre-
quencies. For instance, at 130MHz, the MAX19586
achieves an 82.5dBc SFDR and its SNR performance
stays flat (within 2.5dB) throughout the 4th Nyquist
region. This level of performance makes the part ideal
for high-performance digital receivers.
The MAX19586 operates from a 3.3V analog supply
voltage and a 1.8V digital voltage, features a 2.56V
P-P
full-scale input range, and allows for a guaranteed sam-
pling speed of up to 80Msps. The input track-and-hold
stage operates with a 600MHz full-scale, full-power
bandwidth.
The MAX19586 features parallel, low-voltage CMOS-
compatible outputs in two’s-complement output format.
The MAX19586 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extend-
ed industrial (-40°C to +85°C) temperature range.
Ordering Information
PART
MAX19586ETN
TEMP RANGE
PIN-PACKAGE
PKG
CODE
T5688-2
T5688-2
-40°C to +85°C 56 Thin QFN-EP
MAX19586ETN+ -40°C to +85°C 56 Thin QFN-EP
+Denotes
lead-free package.
Applications
DV
DD
DV
DD
Pin Configuration
TOP VIEW
DGND
DGND
DV
DD
28 AGND
27 REFIN
26 REFOUT
25 AV
DD
24 AV
DD
23 AV
DD
22 AGND
21 AGND
20 AGND
19 AV
DD
18 AV
DD
17 AV
DD
16 N.C.
15 N.C.
1
AV
DD
2
AV
DD
3
AGND
4
CLKP
5
CLKN
6
AGND
7
AGND
8
AGND
9
AGND
10 11 12 13 14
INP
INN
AGND
AGND
AGND
D8
D7
D6
D5
D4
D3
D2
D1
D0
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
High-Performance Instrumentation
Antenna Array Processing
42 41 40 39 38 37 36 35 34 33 32 31 30 29
D9 43
D10 44
D11 45
D12 46
D13 47
D14 48
D15 49
DAV 50
DV
DD
51
DGND 52
DOR 53
N.C. 54
AV
DD
55
AV
DD
56
MAX19586
THIN QFN
8mm x 8mm
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
MAX19586
ABSOLUTE MAXIMUM RATINGS
AV
DD
to AGND ..................................................... -0.3V to +3.6V
DV
DD
to DGND..................................................... -0.3V to +2.4V
AGND to DGND.................................................... -0.3V to +0.3V
INP, INN, CLKP, CLKN, REFP, REFN,
REFIN, REFOUT to AGND....................-0.3V to (AV
DD
+ 0.3V)
D0–D15, DAV, DOR, DAV to GND...........-0.3V to (DV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin Thin QFN
(derate 47.6mW/°C above +70°C) .........................3809.5mW
Operating Temperature Range ..........................-40°C to +85°C
Thermal Resistance
θ
JA
..................................................21°C/W
Thermal Resistance
θ
JC
.................................................0.6°C/W
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD
= 3.3V, DV
DD
= 1.8V, AGND = DGND = 0, INP and INN driven differentially, internal reference CLKP and CLKN driven differentially,
C
L
= 5pF at digital outputs, f
CLK
= 80MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, unless otherwise
noted.) (Note 1)
PARAMETER
DC ACCURACY
Resolution
Offset Error
Gain Error
ANALOG INPUTS (INP, INN)
Input Voltage Range
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
Full-Power Analog Bandwidth
V
DIFF
V
CM
R
IN
C
IN
BW
-3dB
-3dB rolloff for FS Input
Fully differential input, V
IN
= V
INP
- V
INN
Internally self-biased
2.56
2.2
10
±20%
7
600
1.28
±10%
1.28
V
P-P
V
kΩ
pF
MHz
N
VOS
GE
0
-3.5
16
10
20
+3.5
Bits
mV
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUT/OUTPUT (REFIN, REFOUT)
Reference Input Voltage Range
REFIN
V
V
Reference Output Voltage
REFOUT
DYNAMIC SPECIFICATIONS (f
CLK
= 80Msps)
Thermal Plus Quantization Noise
Floor
NF
A
IN
< -35dBFS
f
IN
= 10MHz, A
IN
= -2dBFS
Signal-to-Noise Ratio
(First 4 Harmonics Excluded)
(Notes 2, 3)
f
IN
= 70MHz, A
IN
= -2dBFS
SNR
f
IN
= 100MHz, A
IN
= -2dBFS
f
IN
= 130MHz, A
IN
= -2dBFS
f
IN
= 168MHz, A
IN
= -2dBFS
f
IN
= 10MHz, A
IN
= -2dBFS
Signal-to-Noise Plus Distortion
(Notes 2, 3)
f
IN
= 70MHz, A
IN
= -2dBFS
SINAD
f
IN
= 100MHz, A
IN
= -2dBFS
f
IN
= 130MHz, A
IN
= -2dBFS
f
IN
= 168MHz, A
IN
= -2dBFS
75
77.5
-82
80
79.2
78.5
77.9
77.2
79.6
77.6
77.4
76.4
72.7
dBFS
dB
dB
2
_______________________________________________________________________________________
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 3.3V, DV
DD
= 1.8V, AGND = DGND = 0, INP and INN driven differentially, internal reference CLKP and CLKN driven differentially,
C
L
= 5pF at digital outputs, f
CLK
= 80MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, unless otherwise
noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
f
IN
= 10MHz, A
IN
= -2dBFS
Spurious-Free Dynamic Range
(Worst Harmonic, 2nd and 3rd)
f
IN
= 70MHz, A
IN
= -2dBFS
SFDR1
f
IN
= 100MHz, A
IN
= -2dBFS
f
IN
= 130MHz, A
IN
= -2dBFS
f
IN
= 168MHz, A
IN
= -2dBFS
f
IN
= 10MHz, A
IN
= -2dBFS
Spurious-Free Dynamic Range
(Worst Harmonic, 4th and Higher)
(Note 3)
f
IN
= 70MHz, A
IN
= -2dBFS
SFDR2
f
IN
= 100MHz, A
IN
= -2dBFS
f
IN
= 130MHz, A
IN
= -2dBFS
f
IN
= 168MHz, A
IN
= -2dBFS
f
IN
= 10MHz, A
IN
= -2dBFS
Second-Order Harmonic
Distortion
f
IN
= 70MHz, A
IN
= -2dBFS
HD2
f
IN
= 100MHz, A
IN
= -2dBFS
f
IN
= 130MHz, A
IN
= -2dBFS
f
IN
= 168MHz, A
IN
= -2dBFS
f
IN
= 10MHz, A
IN
= -2dBFS
f
IN
= 70MHz, A
IN
= -2dBFS
Third-Order Harmonic Distortion
HD3
f
IN
= 100MHz, A
IN
= -2dBFS
f
IN
= 130MHz, A
IN
= -2dBFS
f
IN
= 168MHz, A
IN
= -2dBFS
Two-Tone Intermodulation
Distortion
Two-Tone SFDR
CONVERSION RATE
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Jitter
CLOCK INPUTS (CLKP, CLKN)
Differential Input Swing
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
V
DIFFCLK
V
CMCLK
R
INCLK
C
INCLK
DV
DD
-
0.2
0.2
Fully differential inputs
Self-biased
1.0 to
5.0
1.6
10
3
V
P-P
V
kΩ
pF
f
CLKMAX
f
CLKMIN
t
J
0.094
80
20
MHz
MHz
ps
RMS
TTIMD
TTSFDR
f
IN1
= 65.1MHz, A
IN
= -8dBFS
f
IN2
= 70.1MHz, A
IN
= -8dBFS
f
IN1
= 65.1MHz, f
IN2
= 70.1MHz
-100dBFS < A
IN
< -10dBFS
90
80
MIN
TYP
96
84.3
84
82.5
78
102
100
92
94
90
-100
-95
-94
-88.8
-78
-96
-84.3
-84
-82.5
-78
-85.2
99
dBc
dBFS
-80
dBc
-84
dBc
dBc
dBc
MAX
UNITS
MAX19586
CMOS-COMPATIBLE DIGITAL OUTPUTS (D0–D15, DOR, DAV)
Digital Output High Voltage
Digital Output Low Voltage
V
OH
V
OL
I
SOURCE
= 200µA
I
SINK
= 200µA
V
V
_______________________________________________________________________________________
3
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
MAX19586
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 3.3V, DV
DD
= 1.8V, AGND = DGND = 0, INP and INN driven differentially, internal reference CLKP and CLKN driven differentially,
C
L
= 5pF at digital outputs, f
CLK
= 80MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C, unless otherwise
noted.) (Note 1)
PARAMETER
CLKP - CLKN High
CLKP - CLKN Low
Effective Aperture Delay
Output Data Delay
Data Valid Delay
Pipeline Latency
CLKP Rising Edge to DATA Not
Valid
CLKP Rising Edge to DATA
Guaranteed Valid
DATA Setup Time Before Rising
DAV
DATA Hold Time After Rising
DAV
POWER SUPPLIES
Analog Power-Supply Voltage
Digital Output Power-Supply
Voltage
Analog Power-Supply Current
Digital Output Power-Supply
Current
Power Dissipation
AV
DD
DV
DD
I
AVDD
I
DVDD
P
DISS
3.13
1.7
3.3
1.8
320
28
1105
3.46
1.9
382
35
1325
V
V
mA
mA
mW
SYMBOL
t
CLKP
t
CLKN
t
AD
t
DAT
t
DAV
t
P
t
DNV
t
DGV
t
S
t
H
(Note 2)
(Note 2)
Clock duty cycle = 50% (Note 2)
Clock duty cycle = 50% (Note 2)
3
3
1.2
6.5
(Note 2)
2.8
(Note 2)
(Note 2)
CONDITIONS
MIN
5
5
-300
3.3
3.8
7
5.0
TYP
MAX
UNITS
ns
ns
ps
ns
ns
Clock
Cycles
ns
ns
ns
ns
TIMING SPECIFICATION (Figures 4, 5), C
L
= 5pF (D0–D15, DOR); C
L
= 15pF (DAV)
Note 1:
≥
+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.
Note 2:
Parameter guaranteed by design and characterization.
Note 3:
AC parameter measured in a 32,768-point FFT record, where the first 2 bins of the FFT and 2 bins on either side of the carrier
are excluded.
4
_______________________________________________________________________________________
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
MAX19586
Typical Operating Characteristics
(AV
DD
= 3.3V, DV
DD
= 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, C
L
= 5pF at
digital outputs, f
CLK
= 80MHz, T
A
= +25°C. Unless otherwise noted, all AC data based on 32k-point FFT records and under coherent
sampling conditions.)
FFT PLOT
FFT PLOT
FFT PLOT
(32,768-POINT RECORD)
(32,768-POINT RECORD)
(261,244-POINT DATA RECORD)
MAX19586 toc01
MAX19586 toc02
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
0
5
10
15
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
AMPLITUDE (dBFS)
f
CLK
= 80.00012288MHz
f
IN
= 10.10011317MHz
A
IN
= -2.02dBFS
SNR = 80dB
SINAD = 79.8dB
SFDR1 = 96.2dBc
SFDR2 = 101dBc
HD2 = -99.6dBc
HD3 = -96.2dBc
-20
f
CLK
= 80.00012288MHz
f
IN
= 70.16368199MHz
A
IN
= -2.06dBFS
SNR = 79.3dB
SINAD = 77.7dB
SFDR1 = 83.3dBc
SFDR2 = 98.2dBc
HD2 = -93.5dBc
HD3 = -83.3dBc
3
2
-20
-40
-60
-80
-100
-120
-140
f
CLK
= 80.00012288MHz
f
IN
= 130.00050486MHz
A
IN
= -1.82dBFS
SNR = 77.7dB
SINAD = 76.4dB
SFDR1 = 83.1dBc
SFDR2 = 91.2dBc
HD2 = -89.4dBc
HD3 = -83.1dBc
3
2
2
3
20
25
30
35
40
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
CLK
= 80MHz, A
IN
= -2dBFS)
MAX19586toc04
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 80MHz, A
IN
= -2dBFS)
MAX19586toc05
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 80MHz, A
IN
= -2dBFS)
-75
-80
HD2/HD3 (dBc)
HD3
-85
-90
-95
-100
-105
-110
HD2
MAX19586toc06
82
80
SNR
SNR/SINAD (dB)
78
76
74
72
70
0
20
40
60
SINAD
110
105
SFDR1/SFDR2 (dBc)
100
95
90
85
SFDR1
80
75
70
SFDR2
-70
80 100 120 140 160 180
f
IN
(MHz)
0
20
40
60
80 100 120 140 160 180
f
IN
(MHz)
0
20
40
60
80 100 120 140 160 180
f
IN
(MHz)
SNR vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 80MHz, f
IN
= 10.10011MHz)
MAX19586toc07
SFDR1 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 80MHz, f
IN
= 10.10011MHz)
MAX19586toc08
SFDR2 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 80MHz, f
IN
= 10.10011MHz)
MAX19586toc09
85
80
75
SNR (dB, dBFS)
70
65
60
55
50
SNR (dB)
SNR (dBFS)
120
110
SFDR1 (dBc, dBFS)
100
90
SFDR1 (dBc)
80
70
SFDR = 90dB
REFERENCE LINE
SFDR1 (dBFS)
120
110
SFDR2 (dBc, dBFS)
100
90
80
70
60
SFDR = 90dB
REFERENCE LINE
-40
-35
-30
-25
-20
-15
-10
-5
0
SFDR2 (dBc)
SFDR2 (dBFS)
45
40
-40
-35
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT AMPLITUDE (dBFS)
60
-40
-35
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT AMPLITUDE (dBFS)
ANALOG INPUT AMPLITUDE (dBFS)
_______________________________________________________________________________________
MAX19586 toc03
0
0
0
5
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