Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
RevNo.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics.
1.3 Changed I
SB1
to 20mA
Relax D.C parameters.
Item
I
CC
12ns
15ns
20ns
Previous
160mA
155mA
150mA
Current
195mA
190mA
185mA
Final
Draft Data
Feb. 12. 1999
Mar. 29. 1999
Remark
Preliminary
Preliminary
Rev. 2.0
Aug. 19. 1999
Preliminary
Rev. 3.0
3.1 Delete Preliminary
3.2 Update D.C parameters and 10ns part.
I
CC
-
195mA
190mA
185mA
Previous
I
sb
70mA
I
sb1
20mA
I
CC
155mA
145mA
135mA
125mA
Current
I
sb
60mA
I
sb1
10mA
Mar. 27. 2000
10ns
12ns
15ns
20ns
Rev. 4.0
Add Low Power-Ver.
Apr. 24. 2000
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 4.0
April 2000
PRELIMINARY
KM68V4002C/CL, KM68V4002CI/CLI
512K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 60mA(Max.)
(CMOS) : 10mA(Max.)
1.2mA(Max.) L-Ver. only
Operating
KM68V4002C/CL-10 : 155mA(Max.)
KM68V4002C/CL-12 : 145mA(Max.)
KM68V4002C/CL-15 : 135mA(Max.)
KM68V4002C/CL-20 : 125mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention ; L-Ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM68V4002CJ : 36-SOJ-400
KM68V4002CT : 44-TSOP2-400BF
CMOS SRAM
GENERAL DESCRIPTION
The KM68V4002C is a 4,194,304-bit high-speed Static Random
Access Memory organized as 524,288 words by 8 bits. The
KM68V4002C uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM68V4002C is packaged
in a 400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
I/O
1
~I/O
8
ORDERING INFORMATION
KM68V4002C/CL-10/12/15/20
Commercial Temp.
Industrial Temp.
KM68V4002CI/CLI-10/12/15/20
Pre-Charge Circuit
Row Select
Memory Array
1024 Rows
512 x 8 Columns
Data
Cont.
CLK
Gen.
I/O Circuit
Column Select
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
CS
WE
OE
-2-
Rev 4.0
April 2000
PRELIMINARY
KM68V4002C/CL, KM68V4002CI/CLI
PIN CONFIGURATION
(Top View)
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
Vcc
Vss
1
2
3
4
5
6
7
8
9
10
36 N.C
35 A
18
34 A
17
33 A
16
32 A
15
31
OE
N.C
N.C
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
1
2
3
4
5
6
7
8
9
44 N.C
43 N.C
42 N.C
41
40
39
38
37
A
18
A
17
A
16
A
15
OE
CMOS SRAM
30 I/O
8
29 I/O
7
36 I/O
8
35 I/O
7
36-SOJ
I/O
2
10
Vcc 11
Vss 12
I/O
3
13
I/O
4
14
WE
A
5
A
6
A
7
A
8
A
9
15
16
17
18
19
20
28 Vss
27 Vcc
26 I/O
6
25 I/O
5
24 A
14
23 A
13
22 A
12
21 A
11
20 A
10
19 N.C
44-TSOP2
34 Vss
33 Vcc
32 I/O
6
31 I/O
5
30
29
28
27
26
A
14
A
13
A
12
A
11
A
10
I/O
3
11
I/O
4
12
WE
A
5
A
6
A
7
A
8
A
9
13
14
15
16
17
18
25 N.C
24 N.C
23 N.C
N.C 21
N.C 22
PIN FUNCTION
Pin Name
A
0
- A
18
WE
CS
OE
I/O
1
~ I/O
8
V
CC
V
SS
N.C
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
-3-
Rev 4.0
April 2000
PRELIMINARY
KM68V4002C/CL, KM68V4002CI/CLI
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3**
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3***
0.8
Unit
V
V
V
V
CMOS SRAM
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA.
*** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Com.
10ns
12ns
15ns
20ns
Ind.
10ns
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
Norrmal
L-Ver.
Test Conditions
Min
-2
-2
-
-
-
-
-
-
-
-
-
-
-
-
2.4
Max
2
2
155
145
135
125
170
160
150
140
60
10
1.2
0.4
-
V
V
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
7
Unit
pF
pF
-4-
Rev 4.0
April 2000
PRELIMINARY
KM68V4002C/CL, KM68V4002CI/CLI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
*The above test conditions are also applied at industrial temperature range.
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+3.3V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
353Ω
319Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address
Chip Selection to Power Up Time
Chip Selection to Power Down-
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
KM68V4002C-10
KM68V4002C-12
KM68V4002C-15
KM68V4002C-20
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
10
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
6
-
-
12
Min
15
-
-
-
3
0
0
0
3
0
-
Max
-
15
15
7
-
-
7
7
-
-
15
Min
20
-
-
-
3
0
0
0
3
0
-
Max
-
20
20
9
-
-
9
9
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
1 Introduction
In the mid-1960s, American scientist Maas conducted extensive experimental research on the charging process of open-cell batteries and proposed an acceptable charging curve for ...[详细]
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