SSRAM
AS5SP512K36
Plastic Encapsulated Microcircuit
18Mb, 512K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
Synchronous Operation in relation to the input Clock
2 Stage Registers resulting in Pipeline operation
On chip address counter (base +3) for Burst operations
Self-Timed Write Cycles
On-Chip Address and Control Registers
Byte Write support
Global Write support
On-Chip low power mode [powerdown] via ZZ pin
Interleaved or Linear Burst support via Mode pin
Three Chip Enables for ease of depth expansion without
Data Contention.
Two Cycle load, Single Cycle Deselect
Asynchronous Output Enable (OE\)
Three Pin Burst Control (ADSP\, ADSC\, ADV\)
3.3V Core Power Supply
3.3V/2.5V IO Power Supply
JEDEC Standard 100 pin TQFP Package
Available in
Industrial, Enhanced,
and
Mil-
Temperature
Operating Ranges
TQFP
in copper lead frame for superior thermal
performance
RoHs
compliant options available
100-PIN TQFP
PINOUT
(3-CHIP ENABLE)
Fast Access Times
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
Units
ns
ns
ns
GENERAL DESCRIPTION
The AS5SP512K36 is a 18Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High
Performance CMOS technology and is organized as a 512K
x 36. It integrates address and control registers, a two (2)
bit burst address counter supporting four (4) double-word
transfers. Writes are internally self-timed and synchronous
to the rising edge of clock.
Block Diagram
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
CONTROL
BLOCK
I/O Gating and Control
Memory Array
x36
SBP
❑
Synchronous Pipeline
Burst
❋
Two (2) cycle load
❋
One (1) cycle
de-select
❋
One (1) cycle latency
on Mode change
Output
Register
Output
Driver
Input
Register
The AS5SP512K36 includes advanced control options
including Global Write, Byte Write as well as an
Asynchronous Output enable. Burst Cycle controls are
handled by three (3) input pins, ADV, ADSP\ and ADSC\.
Burst operation can be initiated with either the Address
Status Processor (ADSP\) or Address Status Cache
DQx, DQPx
controller (ADSC\) inputs. Subsequent burst addresses
are generated internally in the system’s burst sequence
control block and are controlled by Address Advance (ADV)
control input.
Micross Components reserves the right to change products or specifications without notice.
AS5SP512K36
Rev. 2.9 09/11
1
SSRAM
AS5SP512K36
Fast Access Times
Clock
Address
Address
CLK
A0, A1
A
Input
Input
Input(s)
89
37, 36
35, 34, 33, 32, 100,
99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43, 42
98, 92
97
88
93, 94, 95, 96
87
86
85
This input registers the address, data, enables, Global and Byte
writes as well as the burst control functions
Low order, Synchronous Address Inputs and Burst counter
address inputs
Synchronous Address Inputs
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Byte Write Enable
Output Enable
Address Strobe Controller
CE1\, CE3\
CE2
GW\
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
Input
Input
Input
Input
Input
Input
Input
Active Low True Chip Enables
Active High True Chip Enable
Active Low True Global Write enable. Write to all bits
Active Low True Byte Write enables. Write to byte segments
Active Low True Byte Write Function enable
Active Low True Asynchronous Output enable
Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Bur
When ADSP\ and ADSC are both asserted, only ADSP is recognized
Synchronous Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
Advance input Address. When asserted LOW, address in burst
counter is incremented.
Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
Bidirectional I/O Parity lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Bidirectional I/O Data lines. As inputs they reach the memo
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Interleaved or Linear Burst mode control
Core Power Supply
Core Power Supply Ground
Isolated Input/Output Buffer Supply
Isolated Input/Output Buffer Ground
No connections to internal silicon
Address Strobe from Processor
ADSP\
Input
84
Address Advance
Power-Down
Data Parity Input/Outputs
ADV\
ZZ
DQPa, DQPb
DQPc, DQPd
Input
Input
Input/
Output
83
64
51, 80, 1, 30
Data Input/Outputs
DQa, DQb, DQc
DQd
Input/
Output
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
I/O Ground
No Connection(s)
MODE
VDD
VSS
VDDQ
VSSQ
NC
Input
Supply
Supply
Supply
Supply
NA
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6,
7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
31
91, 15, 41, 65
90, 17, 40, 67
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
71, 76
14, 16, 38, 39, 66
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
ADSC
ADSP
BW
D
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
BURST
COUNTER
CLR
AND
LOGIC
Q0
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
B
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
AS5SP512K36
Rev. 2.9 09/11
Micross Components reserves the right to change products or specifications without notice.
2
SSRAM
AS5SP512K36
Functional Description
Micross Components AS5SP512K36 Synchronous SRAM is
manufactured to support today’s High Performance platforms
utilizing the Industries leading Processor elements including
those of Intel and Motorola. The AS5SP512K36 supports
Synchronous SRAM READ and WRITE operations as well as
Synchronous Burst READ/WRITE operations. All inputs with
the exception of OE\, MODE and ZZ are synchronous in nature
and sampled and registered on the rising edge of the devices
input clock (CLK). The type, start and the duration of Burst
Mode operations is controlled by MODE, ADSC\, ADSP\ and
ADV as well as the Chip Enable pins CE1\, CE2, and CE3\.
All synchronous accesses including the Burst accesses are
enabled via the use of the multiple enable pins and wait state
insertion is supported and controlled via the use of the Advance
control (ADV).
The AS5SP512K36 supports both Interleaved as well as Linear
Burst modes therefore making it an architectural fit for either
the Intel or Motorola CISC processor elements available on
the Market today.
The AS5SP512K36 supports Byte WRITE operations and
enters this functional mode with the Byte Write Enable (BWE\)
and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\).
Global Writes are supported via the Global Write Enable (GW\)
and Global Write Enable will override the Byte Write inputs
and will perform a Write to all Data I/Os.
The AS5SP512K36 provides ease of producing very dense
arrays via the multiple Chip Enable input pins and Tri-state
outputs.
Single Cycle Access Operations
A Single READ operation is initiated when all of the following
conditions are satisfied at the time of Clock (CLK) HIGH: [1]
ADSP\ pr ADSC\ is asserted LOW, [2] Chip Enables are all
asserted active, and [3] the WRITE signals (GW\, BWE\) are in
their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH.
The address presented to the Address inputs is stored within
the Address Registers and Address Counter/Advancement
Logic and then passed or presented to the array core. The
corresponding data of the addressed location is propagated to
the Output Registers and passed to the data bus on the next
rising clock via the Output Buffers. The time at which the data
is presented to the Data bus is as specified by either the Clock
to Data valid specification or the Output Enable to Data Valid
spec for the device speed grade chosen. The only exception
occurs when the device is recovering from a deselected to select
state where its outputs are tristated in the first machine cycle
and controlled by its Output Enable (OE\) on following
AS5SP512K36
Rev. 2.9 09/11
cycle. Consecutive single cycle READS are supported. Once
the READ operation has been completed and deselected by use
of the Chip Enable(s) and either ADSP\ or ADSC\, its outputs
will tri-state immediately.
A Single ADSP\ controlled WRITE operation is initiated
when both of the following conditions are satisfied at the time
of Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2]
Chip Enable(s) are asserted ACTIVE. The address presented
to the address bus is registered and loaded on CLK HIGH, then
presented to the core array. The WRITE controls Global Write,
and Byte Write Enable (GW\, BWE\) as well as the individual
Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are
ignored on the first machine cycle. ADSP\ triggered WRITE
accesses require two (2) machine cycles to complete. If Global
Write is asserted LOW on the second Clock (CLK) rise, the
data presented to the array via the Data bus will be written into
the array at the corresponding address location specified by
the Address bus. If GW\ is HIGH (inactive) then BWE\ and
one or more of the Byte Write controls (BWa\, BWb\, BWc\
and BWd\) controls the write operation. All WRITES that are
initiated in this device are internally self timed.
A Single ADSC\ controlled WRITE operation is initiated when
the following conditions are satisfied: [1] ADSC\ is asserted
LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s)
are asserted (TRUE or Active), and [4] the appropriate
combination of the WRITE inputs (GW\, BWE\, BWx\)
are asserted (ACTIVE). Thus completing the WRITE to the
desired Byte(s) or the complete data-path. ADSC\ triggered
WRITE accesses require a single clock (CLK) machine cycle
to complete. The address presented to the input Address bus
pins at time of clock HIGH will be the location that the WRITE
occurs. The ADV pin is ignored during this cycle, and the
data WRITTEN to the array will either be a BYTE WRITE
or a GLOBAL WRITE depending on the use of the WRITE
control functions GW\ and BWE\ as well as the individual
BYTE CONTOLS (BWx\).
Deep Power-Down Mode (SLEEP)
The AS5SP512K36 has a Deep Power-Down mode and is
controlled by the ZZ pin. The ZZ pin is an Asynchronous
input and asserting this pin places the SSRAM in a deep power-
down mode (SLEEP). White in this mode, Data integrity is
guaranteed. For the device to be placed successfully into this
operational mode the device must be deselected and the Chip
Enables, ADSP\ and ADSC\ remain inactive for the duration
of tZZREC after the ZZ input returns LOW. Use of this deep
power-down mode conserves power and is very useful in
multiple memory page designs where the mode recovery time
can be hidden.
Micross Components reserves the right to change products or specifications without notice.
3
SSRAM
AS5SP512K36
Synchronous Truth Table
CE1\
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
Notes:
1. X = Don’t Care
2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE
CE2
X
L
X
L
X
H
H
H
X
X
X
X
X
X
X
X
CE3\
X
X
H
X
H
L
L
L
X
X
X
X
X
X
X
X
ADSP\
X
L
L
X
X
L
H
H
H
X
H
X
H
X
H
X
ADSC\
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
ADV\
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
WT / RD
X
X
X
X
X
X
WT
RD
RD
RD
WT
WT
RD
RD
WT
WT
CLK
Address Accessed
NA
NA
NA
NA
NA
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Operation
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst, READ
Begin Burst, WRITE
Begin Burst, READ
Continue Burst, READ
Continue Burst, READ
Continue Burst, WRITE
Continue Burst, WRITE
Suspend Burst, READ
Suspend Burst, READ
Suspend Burst, WRITE
Suspend Burst, WRITE
Burst Sequence Tables
Burst Control
Pin [MODE]
First Address
State
HIGH
Case 1
A1
0
0
1
1
A0
Interleaved Burst
Case 2
A1
A0
0
0
1
0
0
1
1
1
Linear Burst
Case 2
A1
A0
0
1
1
0
Case 3
A1
1
0
1
0
1
1
0
0
A0
0
1
0
1
A1
1
1
0
0
Case 4
A0
1
0
1
0
Capacitance
Parameter
Input Capacitance
Input/Output Capacitance
Clock Input Capacitance
Symbol
CI
CIO
CCLK
Max.
6
8
6
Units
pF
pF
pF
Fourth Address
Burst Control
Pin [MODE]
First Address
State
LOW
Case 1
A1
0
0
1
1
A0
0
1
0
1
Case 3
A1
1
0
1
0
1
1
0
0
A0
0
1
0
1
A1
Case 4
A0
1
0
0
1
1
0
1
0
Fourth Address
Write Table
GW\
H
H
H
H
H
H
L
BW\
H
L
L
L
L
L
X
BWa\
X
H
L
H
H
L
X
BWb\
X
H
H
L
H
L
X
BWc\
X
H
H
H
L
L
X
BWd\
X
H
H
H
L
L
X
Operation
READ
READ
WRITE Byte [A]
WRITE Byte [B]
WRITE Byte [C], [D]
WRITE ALL Bytes
WRITE ALL Bytes
Asynchronous Truth Table
Operation
Power-Down (SLEEP)
READ
WRITE
De-Selected
ZZ
H
L
L
L
L
OE\
X
L
H
X
X
I/O Status
High-Z
DQ
High-Z
Din, High-Z
High-Z
Absolute Maximum Ratings*
Parameter
Voltage on VDD Pin
Voltage on VDDQ Pins
Voltage on Input Pins
Voltage on I/O Pins
Power Dissipation
Storage Temperature
Operating Temperatures
[Screening Levels]
Symbol
VDD
VDDQ
VIN
VIO
PD
tSTG
/IT
/ET
/XT
Min.
-0.3
VDD
-0.3
-0.3
-65
-40
-40
-55
VDD+0.3
VDDQ+0.3
1.6
150
85
105
125
AC Test Loads
Max.
4.6
Units
V
V
V
V
W
C
C
C
C
Output
Zo=50 ohm
Diagram [A]
30 pF
Vt= 1.50v for 3.3v VDDQ
Vt= 1.25v for 2.5v VDDQ
Rt = 50 ohm
Vt= Termination Voltage
Rt= Termination Resistor
*Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum conditions for any duration or
segment of time may affect device reliability.
AS5SP512K36
Rev. 2.9 09/11
R= 317 ohm@3.3v
R= 1667 ohm@2.5v
3.3/2.5v
5 pF
R= 351 ohm@3.3v
R= 1538 ohm@2.5v
Diagram [B]
Output
Micross Components reserves the right to change products or specifications without notice.
4
SSRAM
AS5SP512K36
DC Electrical Characteristics
(VDD=3.3v ± 5%,
TA=Min. and Max temperatures of Screening level chosen
Symbol
VDD
VDDQ
VoH
VoL
VIH
VIL
IIL
IZZL
IOL
IDD
Parameter
Power Supply Voltage
I/O Supply Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage (except ZZ)
Input Leakage, ZZ pin
Output Leakage
Operating Current
VDD=Max., VIN=VSS to VDD
Output Disabled, VOUT=VSSQ to VDDQ
VDD=Max., f=Max.,
IOH=0mA
Test Conditions
VDD=Min., IOH=-4mA
VDD=Min., IOH=-1mA
VDD=Min., IOL=8mA
VDD=Min., IOL=1mA
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
Min
3.135
2.375
2.4
2
Max
3.630
VDD
2
1.7
-0.3
-0.3
-5
-30
-5
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
0.4
0.4
VDD+0.3
VDD+0.3
0.8
0.7
5
30
5
475
425
375
250
225
200
200
250
Units
V
V
V
V
V
V
V
V
V
V
uA
uA
uA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1
1,5
1,4
1,4
1,4
1,4
1,2
1,2
1,2
1,2
3
3
ISB1
Automatic CE, Power Down
Current - TTL inputs
Max VDD, De-Selected,
VIN>=VIH or VIN</=VIL
f=0=1/tCYC
ISB2
ISB3
CMOS Standby
TTL Standby
Max. VDD, Device deselected, VIN </=0.3V or VIN>/=VDDQ-0.3V
f=fMAX=1/tCYC
Device deselected; VDD=Max.; All Inputs </= VIL or VIH;
All inputs static; CLK frequency = f
MAX
Thermal Resistance
Parameter
JA
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
DQ
DQC
Package Package Unit
28.66
4.08
30.2
6.5
o
C/W
C/W
o
Notes:
[1]
[2]
All Voltages referenced to VSS (Logic Ground)
Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA
Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA
Power-up: VIH <+3.6V and VDD<3.135V for t<200ms
MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA
The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies.
AC load current is higher than stated values, AC I/O curves can be made available upon request
VDDQ should never exceed VDD, VDD and VDDQ can be connected together
This parameter is sampled
[3]
[4]
[5]
[6]
AS5SP512K36
Rev. 2.9 09/11
Micross Components reserves the right to change products or specifications without notice.
5
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