MGA-65606
Low Noise Amplifier with switchable Bypass/Shutdown Mode
in Low Profile Package
Data Sheet
Description
Avago Technologies’ MGA-65606 is an economical, easy-
to-use GaAs MMIC Low Noise Amplifier (LNA) with Bypass/
Shutdown mode. The LNA has low noise and high linearity
achieved through the use of Avago Technologies’ propri-
etary 0.25
m
GaAs Enhancement-mode pHEMT process.
The Bypass/Shutdown mode enables the LNA to be
bypassed during high input signal power and reduce
current consumption. It is housed in a low profile 2.0 x 1.3
x 0.5 mm
3
6-pin Ultra Thin Package. The compact footprint
and low profile coupled with low noise, high linearity make
the MGA-65606 an ideal choice as a low noise amplifier for
mobile and CPE receivers in the WiMAX and WLL (2.5 – 4)
GHz band.
Features
Low current consumption
Adjustable bias current
Simple matching network
Broadband operation (2.5 – 4) GHz
Low Noise Figure
Low current consumption in Bypass Mode, <100
A
Fully matched to 50 ohm in Bypass Mode
High Linearity (LNA and Bypass Mode)
Low profile package
Typical Performance
3.5 GHz; 3V, 10mA (Typ):
15.3 dB Gain
1.05 dB Noise Figure
+5.7 dBm Input IP3
-2.4 dBm Input Power at 1 dB gain compression
4.2 dB Insertion Loss in Bypass Mode
17 dBm IIP3 in Bypass Mode (Pin = -20 dBm)
<100
A
current consumption in Bypass mode
Component Image
2.0 x 1.3 x 0.5 mm
3
6-lead Ultra Thin Package
Note:
Package marking provides
orientation and identification
“65” = Product Code
“X” = Month Code
65X
Pin Configuration
Pin 1 (Vbias)
Pin 2 (RFin)
Pin 3 (Gnd)
TOP VIEW
GND
Pin 6 (Vsd)
Pin 5 (RFOut)
Pin 4 (Vdd)
Applications
Low noise amplifier for WiMAX, Wireless Local Loop.
Other ultra low noise applications in the 2.5 – 4 GHz
band.
Simplified Schematic
R
VBias
RF
IN
L
3
LNA
4
1
Bias /
Control
6
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 50 V
ESD Human Body Model = 300 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
VSD
L
RF OUT
L
C
R
Vdd
C
2
5
Absolute Maximum Rating
[1]
T
A
= 25° C
Symbol
V
dd
Vbias
P
in,max
P
diss
T
j
T
STG
Thermal Resistance
Units
V
V
dBm
mW
°C
°C
Parameter
Device Voltage, RF Output to Ground
Control Voltage
CW RF Input Power
Total Power Dissipation
Junction Temperature
Storage Temperature
Absolute Maximum
5
(Vdd-0.3)
+12
104
150
-65 to 150
Thermal Resistance
[2,3]
(V
dd
= 3.0 V, Id = 10 mA),
jc
= 80° C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Thermal resistance measured using Infra-Red
Measurement Technique.
3. Board temperature (T
b
) is 25° C, for T
b
>146° C,
derate the device power at 14 mW per °C
rise in Board (pakcage belly) temperature.
Product Consistency Distribution charts
[1]
LSL
USL
USL
13
14
15
16
17
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Figure 1. Gain @ 3.5 GHz,Vdd 3V; Vbias 2.7 V
LSL = 14 dB, Nominal = 15.3 dB, USL = 17 dB
Figure 2. NF @ 3.5 GHz,Vdd 3 V; Vbias 2.7 V
Nominal = 1.05 dB, USL = 1.35 dB
USL
Note:
1. Distribution data sample size is 3000 samples taken from 3 different
wafers and 3 different lots. Future wafers allocated to this product
may have nominal values anywhere between the upper and lower
limits.
7
8
9
10
11
12
13
Figure 3. Idd @ 3.5 GHz,Vdd 3 V; Vbias 2.7 V
Nominal = 10.0 mA, USL = 12.0 mA
2
Electrical Specifications
[1]
T
A
= 25° C, Vdd =3 V, Vbias = 2.7 V, RF measurement at 3.5 GHz – Typical Performance
Symbol
Idd
Gain
NF
IIP3
IP1dB
S11
S22
S12
|S21|
BYPASS
IIP3
BYPASS
Idd
BYPASS
|S21|
SHUTDOWN
Idd
SHUTDOWN
Parameter and Test Condition
Bias Current
Gain
Noise Figure
Input Third Order Intercept Point
Input Power at 1 dB Gain Compression
Input Return Loss, 50
source
Output Return Loss, 50
load
Reverse Isolation
Bypass Mode Insertion Loss
Bypass Mode IIP3 (Tested at -20 dBm input Power)
Bypass Mode Current
Shutdown Mode Isolation
Shutdown Mode Current
Units
mA
dB
dB
dBm
dBm
dB
dB
dB
dB
dBm
A
dB
A
Min.
–
14
–
–
–
–
–
–
–
–
–
–
–
Typ.
10
15.3
1.05
+5.7
-2.4
-13.6
-11
-24
4.2
17
70
17
105
Max.
12
17
1.35
–
–
–
–
–
–
–
–
–
–
LNA Mode performance ( Vdd = 3 V,Vbias = 2.7 V & VSD = 0 V)
BYPASS Mode performance ( Vdd = 3 V, Vbias = 0 V & VSD = 0 V)
Shutdown Mode performance ( Vdd = 3 V,Vbias = 0 V & VSD = 3 V)
Note:
1. 3.5 GHz IIP3 test condition: F
RF1
= 3.5 GHz, F
RF2
= 3.505 GHz with input power of -20 dBm per tone.
Table 1. LNA Switch Truth Table
Vbias (V) / Vsd (V)
2.7 / 0
[1]
0 / 0
[2]
0 / 3
[3]
Vdd (V)
3
3
3
Mode
LNA
BYPASS
SHUTDOWN
Notes:
1. Device operation in LNA mode if Vbias > 2.2 V and Vsd < 0.5 V. Bias current of LNA can be varied
with different values of Vbias for Vbias > 2.2 V. See Fig 5 below.
2. Device operation in BYPASS mode if Vbias < 0.3 V and VSD < 0.5 V.
3. Device is shutdown if Vsd >2.6 V. In SHUTDOWN mode, LNA and internal Bypass switch is turn
OFF. SHUTDOWN mode override Vbias voltage setting. Pin 6 (Vsd) is a Pull-Down logic function
pin and recommend to ground it if shutdown function is not used in application.
3
Demo Board Layout
GND
1
GND
OCT 2010
Avago
Technologies
Vbias
2
Vbias
GND
3
GND
Vsd
4
Vsd
Vdd
5
Vdd
GND
6
GND
MIMOSA v2
RF Input
IN
L1
RF Output
OUT
L2
R2
L3
C1
R1
C2
Figure 4. Demo Board Layout Diagram
Application Notes
1. Performance in a specified frequency band can be optimized by changing component values in the demo board
above to suit the application at that frequency. The schematic on page 5 show components used to demonstrate
performance at the (3.0 – 4.0) GHz band.
2. Pin1 (Vbias pin) voltage in LNA mode can be varied to enable the LNA bias current to be adjusted, refer to next
graph:
12.0
10.0
8.0
Id (mA)
6.0
4.0
2.0
0.0
2.0
2.1
2.2
2.3
2.4
2.5 2.6
Vbias (V)
2.7
2.8
2.9
3.0
Figure 5. Id vs Vbias (Vdd = 3 V; Vsd = 0 V). Vbias is varies in this plot.
4
Demo Board Schematic for 3.5 GHz application
V Bias
(Pin 1)
RF
IN
(Pin
2)
50-Ohms
TL
R2
1
Bias /
Control
6
VSD
(Pin
6)
L2
50-Ohms
TL
2
L1
LNA
3
5
RF OUT
(Pin
5)
L3
4
C1
R1
C2
Vdd
(Pin
4)
Gnd
(Pin
3)
Figure 6. Demo Board Schematic Diagram
Table 2 Typical Components Used For Demo Board In Fig 4
And Schematic Shown In Fig 6. R2 is adjusted for desired
current.
Component
L1
L2
L3
C1
C2
R1
R2
MGA-65606 Typical Performance (3.5 GHz match)
T
A
= +25° C, V
dd
= 3 V, I
ds
= 10 mA (Vbias = 2.7 V), RF mea-
surement at 3.5 GHz, Input Signal = CW unless stated
otherwise.
20
10
0
-10
dB
-20
-30
-40
-50
-60
1.0
1.5
2.0
2.5
3.0 3.5 4.0
Frequency (GHz)
4.5
5.0
5.5
6.0
Input Return Loss
Output Return Loss
Gain
Isolation
Vendor
Taiyo Yuden
Taiyo Yuden
Taiyo Yuden
Taiyo Yuden
Murata
ROHM
ROHM
Size
0402
0402
0402
0402
0402
0402
0402
Value
2.2 nH
2.4 nH
1.0 nH
8 pF
0.1
F
10 ohm
1.8 Kohm
Figure 7. LNA Mode Gain, Input Return Loss, Output Return Loss, Isolation vs
Frequency
5
FPGA/CPLD
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