MGA-43428
High Linearity 851 – 894 MHz Power Amplifier Module
Data Sheet
Description
Avago Technologies’ MGA-43428 is a fully matched
power amplifier for use in the (851-894) MHz band. High
linear output power at 5V is achieved through the use of
Avago Technologies’ proprietary 0.25um GaAs Enhance-
ment-mode pHEMT process. MGA-43428 is housed in a
miniature 5.0mm x 5.0mm molded-chip-on-board (MCOB)
module package. A detector is also included on-chip. The
compact footprint coupled with high gain, high linearity
and good efficiency makes the MGA-43428 an ideal choice
as a power amplifier for small cell BTS PA applications.
Features
•
High linearity performance : Max -50dBc ACLR
[1]
at
27.2dBm linear output power (biased on 5V supply)
•
High gain : 33.7dB
•
Good efficiency
•
Fully matched
•
Built-in detector
•
GaAs E-pHEMT Technology
[2]
•
Low cost small package size: (5.0 x 5.0 x 0.9) mm
•
MSL3
•
Lead free/Halogen free/RoHS compliance
Applications
•
Final stage high linearity amplifier for Picocell and
Enterprise Femtocell PA targeted for small cell BTS
downlink applications.
Specifications
880MHz; 5.0V, Idqtotal =350mA (typ), W-CDMA Test model
#1, 64DPCH downlink signal
•
PAE : 14.9%
•
27.2dBm linear Pout @ ACLR = -50dBc
[1]
•
33.7dB Gain
•
Detector range : 20dB
Note:
1. W-CDMA Test model #1, 64DPCH downlink signal.
2. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
Component Image
5.0 x 5.0 x 0.9 mm Package Outline
A
VAGO
Note:
Package marking provides orientation
and identification
“43428 “ = Device part number
“YYWW” = year and work week
“XXXX” = assembly lot number
43428
YYWW
XXXX
TOP VIEW
Pin Configuration
26 Vdd2
24 Vdd3
23 Vdd3
22 Vdd3
27 Gnd
25 Gnd
28 NC
Functional Block Diagram
Vdd2
Vdd3
Gnd 1
Gnd 2
NC 3
RFin 4
NC 5
Gnd 6
NC 7
21 Gnd
20 Gnd
19 RFout
18 RFout
17 RFout
16 Gnd
RFin
2
nd
Stage
3
rd
Stage
RFout
Biasing Circuit
Vc2 Vc3
VddBias
Vdet
(5.0 x 5.0 x 0.9) mm
15 Gnd
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 80 V
ESD Human Body Model = 400 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
NC 8
Vc2 9
Vc3 10
Gnd 11
VddBias 12
Gnd 13
Vdet 14
Absolute Maximum Rating
[1]
T
A
= 25° C
Symbol
Vdd, VddBias
Vc
P
in,max
P
diss
T
j
T
STG
Thermal Resistance
[2,3]
Units
V
V
dBm
W
°C
°C
Parameter
Supply voltages, bias supply voltage
Control Voltage
CW RF Input Power
Total Power Dissipation
[3]
Junction Temperature
Storage Temperature
Absolute Max.
6
(Vdd)
20
4.9
150
-65 to 150
q
jc
= 13.5°C/W
Notes:
1. Operation of this device in excess of any
of these limits may cause permanent
damage.
2. Thermal resistance measured using Infra-
Red Measurement Technique at Vdd =
5.5 V operating voltage.
3. Board temperature (TB) is 25
°C
, for TB
>83.8
°C
derate the device power at
74mW per
°C
rise in Board (package belly)
temperature.
Electrical Specifications
T
A
= 25
°C,
Vdd = VddBias = 5.0V, Vc2=Vc3=3V, Idqtotal = 350mA, RF performance at 880MHz, W-CDMA Test model #1,
64DPCH downlink signal operation unless otherwise stated.
Symbol
Vdd
Idqtotal
Gain
OP1dB
ACLR1 @ Pout = 27.2 dBm
PAE @ Pout = 27.2 dBm
|S11|
DetR
Parameter and Test Condition
Supply Voltage
Quiescent Supply Current
Gain
Output Power at 1dB Gain Compression
W-CDMA Test model #1, 64DPCH downlink signal
Power Added Efficiency
Input Return Loss, 50
Ω
source
Detector RF dynamic range
Units
V
mA
dB
dBm
dBc
%
dB
dB
Min.
-
-
31
-
-
13
-
-
Typ.
5.0
350
33.7
36.4
-50
14.9
25
20
Max.
-
560
-
-
-
-
-
-
T
A
= 25
°C,
Vdd =VddBias=5.5V, Vc2=2.9V, Vc3=2.7V Idqtotal = 345mA, RF performance at 880MHz, W-CDMA Test model
#1, 64DPCH downlink signal operation unless otherwise stated.
Symbol
Vdd
Idqtotal
Gain
OP1dB
ACLR1 @ Pout = 27.9 dBm
PAE @ Pout = 27.9 dBm
|S11|
DetR
Parameter and Test Condition
Supply Voltage
Quiescent Supply Current
Gain
Output Power at 1dB Gain Compression
W-CDMA Test model #1, 64DPCH downlink signal
Power Added Efficiency
Input Return Loss, 50
Ω
source
Detector RF dynamic range
Units
V
mA
dB
dBm
dBc
%
dB
dB
Typ.
5.5
345
33.7
37.0
-50
15
25
20
2
Product Consistency Distribution Charts
[1]
LSL
LSL
30
31
32
33
34
35
36
37
13 13.5 14 14.5
15 15.5
16 16.5 17
Figure 1. Gain at Pout=27.2dBm, LSL= 31dB, nominal = 33.7dB
Figure 2. PAE at Pout=27.2dBm, LSL=13%, nominal = 14.9%
USL
200
250 300 350 400 450 500 550 600
610
630
650
670
690
710
Figure 3. Idqtotal, Nominal = 350mA, USL=560mA
Figure 4. Idd_Total at Pout=27.2dBm, nominal = 670mA
-55
-54
-53
-52
-51
-50
-49
-48
-47
Figure 5. ACLR1 at Pout=27.2dBm, nominal = -51.1dBc
Note:
1. Distribution data sample size is 1500 samples taken from 3 different wafer lots. T
A
= 25
°C,
Vdd=VddBias = 5.0V, Vc2 = Vc3 = 3V, RF performance at
880MHz unless otherwise stated. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits.
3
MGA-43428 typical over-temperature performance at Vc2= Vc3=3V (Vdd=VddBias=5V) as shown in Figure 35 and
Vc2= 2.9V, Vc3=2.7V (Vdd=VddBias=5.5V) unless otherwise stated.
40
30
20
S21,S11,S22/dB
10
0
S22
S11
S21
40
85
°C
25
°C
-40
°C
30
20
S21,S11,S22/dB
10
0
-10
-20
-30
S21
85
°C
25
°C
-40
°C
-10
-20
-30
-40
0.1
0.3
0.5
0.7
S22
S11
0.9 1.1 1.3
Frequency/GHz
1.5
1.7
1.9
2.1
-40
0.1
0.3
0.5
0.7
0.9 1.1 1.3
Frequency/GHz
1.5
1.7
1.9
2.1
Figure 6. Small-signal performance Over-temperature
Vdd=VddBias=5.0V operating voltage
Figure 7. Small-signal performance Over-temperature Vdd=VddBias=5.5V
operating voltage
-35
-40
-45
ACLR1/dBc
-50
-55
-60
-65
19
20
21
22
23
24 25
Pout/dBm
26
27
28
29
ACLR1_85
°C
PAE_85
°C
ACLR1_25
°C
PAE_25
°C
ACLR1_-40
°C
PAE_-40
°C
24
20
16
-35
-40
-45
ACLR1/dBc
-50
-55
-60
-65
19
ACLR1_85
°C
PAE_85
°C
ACLR1_25
°C
PAE_25
°C
ACLR1_-40
°C
PAE_-40
°C
24
20
16
12
8
4
12
8
4
0
30
20
21
22
23
24 25
Pout/dBm
26
27
28
29
0
30
Figure 8. Over-temperature ACLR1, PAE vs Pout @ 851MHz
Vdd=VddBias=5.0V operating voltage
Figure 9. Over-temperature ACLR1, PAE vs Pout @ 859MHz Vdd=VddBias=5V
operating voltage
-35
-40
-45
ACLR1/dBc
-50
-55
-60
-65
19
ACLR1_85
°C
PAE_85
°C
ACLR1_25
°C
PAE_25
°C
ACLR1_-40
°C
PAE_-40
°C
24
20
16
12
8
4
ACLR1/dBc
-35
-40
-45
-50
-55
-60
-65
19
ACLR1_85
°C
PAE_85
°C
ACLR1_25
°C
PAE_25
°C
ACLR1_-40
°C
PAE_-40
°C
24
20
16
12
8
4
20
21
22
23
24 25
Pout/dBm
26
27
28
29
0
30
20
21
22
23
24 25
Pout/dBm
26
27
28
29
0
30
Figure 10. Over-temperature ACLR1, PAE vs Pout @ 869MHz
Vdd=VddBias=5.0V operating voltage
Figure 11. Over-temperature ACLR1, PAE vs Pout @ 869MHz
Vdd=VddBias=5.5V operating voltage
4
MGA-43428 typical over-temperature performance at Vc2= Vc3=3V (Vdd=VddBias=5V) as shown in Figure 35 and
Vc2= 2.9V, Vc3=2.7V (Vdd=VddBias=5.5V) unless otherwise stated.
-35
-40
-45
ACLR1/dBc
-50
-55
-60
-65
19
20
21
22
23
24
25
26
27
28
29
ACLR1_85
°C
PAE_85
°C
ACLR1_25
°C
PAE_25
°C
ACLR1_-40
°C
PAE_-40
°C
24
20
16
ACLR1/dBc
12
8
4
0
30
-35
-40
-45
-50
-55
-60
-65
19
20
21
22
23
24
25
26
27
28
29
ACLR1_85
°C
PAE_85
°C
ACLR1_25
°C
PAE_25
°C
ACLR1_-40
°C
PAE_-40
°C
24
20
16
12
8
4
0
30
Pout/dBm
Pout/dBm
Figure 12. Over-temperature ACLR1, PAE vs Pout @ 880MHz
Vdd=VddBias=5.0V operating voltage
-35
-40
-45
ACLR1/dBc
-50
-55
-60
-65
19
20
21
22
23
24 25
Pout/dBm
26
27
28
29
24
20
16
12
8
4
0
30
Figure 13. Over-temperature ACLR1, PAE vs Pout @ 880MHz
Vdd=VddBias=5.5V operating voltage
-35
-40
-45
ACLR1/dBc
-50
-55
-60
-65
19
20
21
22
23
24 25 26
Pout/dBm
27
28
29
24
20
16
12
8
4
0
30
ACLR1_85
°C
PAE_85
°C
ACLR1_25
°C
PAE_25
°C
ACLR1_-40
°C
PAE_-40
°C
ACLR1_85
°C
PAE_85
°C
ACLR1_25
°C
PAE_25
°C
ACLR1_-40
°C
PAE_-40
°C
Figure 14. Over-temperature ACLR1, PAE vs Pout @ 894MHz
Vdd=VddBias=5.0V operating voltage
Figure 15. Over-temperature ACLR1, PAE vs Pout @ 894MHz
Vdd=VddBias=5.5V operating voltage
1200
1100
1000
900
Idd total/mA
800
700
600
500
400
300
19
20
21
22
23
24
25
Pout/dBm
26
27
28
29
30
Idd_Total_85
°C
Idd_Total_25
°C
Idd_Total_-40
°C
1200
1100
1000
Idd_Total_85
°C
Idd_Total_25
°C
Idd_Total_-40
°C
Idd total/mA
900
800
700
600
500
400
300
19
20
21
22
23
24
25
26
27
28
29
30
Pout/dBm
Figure 16. Over-temperature Idd_Total vs Pout @ 880MHz
Vdd=VddBias=5.0V operating voltage
Figure 17. Over-temperature Idd_Total vs Pout @ 880MHz
Vdd=VddBias=5.5V operating voltage
5
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