AS4SD8M16
128 Mb: 8 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full Military temp (-55°C to 125°C) processing available
Copper lead frame option for enhanced reliability
Configuration: 8 Meg x 16 (2 Meg x 16 x 4 banks)
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
Self Refresh Mode (IT & ET)
64ms, 4,096-cycle refresh (IT)
24ms 4,096 cycle recfresh (XT)
WRITE Recovery (t
WR
= “2 CLK”)
LVTTL-compatible inputs and outputs
Single +3.3V ±0.3V power supply
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
V
DD
DQML
WE\
CAS\
RAS\
CS\
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
V
SS
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
SDRAM
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
OPTIONS
•
MARKING
Plastic Package –54-pin TSOPII (400 mil)
- Alloy 42 lead frame - OCPL*
DG No. 901
- Copper lead frame
DGC
(Pb/Sn
fi
nish or RoHS available)
•
Timing (Cycle Time)
7.5ns @ CL = 3 (PC133) or
7.5ns @ CL = 2 (PC100)
Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C)
-Enhanced Temp
(-40°C to +105°C)
-Military Temp (-55°C to 125°C)
-75
•
IT
ET
XT
8 Meg x 16
Configuration
2 Meg x 16 x 4 banks
Refresh Count
4K
Row Addressing
4K (A0-A11)
Bank Addressing
4 (BA0, BA1)
Column Addressing
512 (A0-A8)
Note: “\” indicates an active low.
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
GRADE FREQUENCY CL = 2** CL = 3**
-75
133 MHz
–
5.4ns
-75
100 MHz
6ns
–
*Off-center parting line
**CL = CAS (READ) latency
SETUP
TIME
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
For more products and information
please visit our web site at
www.micross.com
Micross Components reserves the right to change products or specifications without notice.
AS4SD8M16
Rev. 1.1 04/10
1
AS4SD8M16
GENERAL DESCRIPTION
The 128Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 134, 217, 728 bits. It is
internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 33, 554,
432-bit banks is organized as 4,096 rows by 512 columns by
16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The address bits
registered coincident with the READ or WRITE command
are used to select the starting column location for the burst
access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page,
with a burst terminate option. An auto precharge function may
be enabled to provide a self-timed row precharge that is initiated
at the end of the burst sequence.
The 128Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed, fully
random operation. Precharging one bank while accessing one of
the other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
The 128Mb SDRAM is designed to operate in 3.3V mem-
ory systems. An auto refresh mode is provided, along with a
power-saving, power-down mode. All inputs and outputs are
LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating
performance, including the ability to synchronously burst data at
a high data rate with automatic column-address generation, the
ability to interleave between internal banks to hide precharge
time and the capability to randomly change column addresses
on each clock cycle during a burst access.
SDRAM
FUNCTIONAL BLOCK DIAGRAM
AS4SD8M16
Rev. 1.1 04/10
Micross Components reserves the right to change products or specifications without notice.
2
AS4SD8M16
ENHANCING RELIABILITY WITH COPPER LEAD FRAMES
1
ADVANTAGES & BENEFITS
Superior thermal conductivity improvement: 170 W/m*K
vs. 14 W/m*K (a 12X difference).
•
θ
ja and
θ
jc characteristics provide up to 3.8X advantage
of heat dissipation capability versus parts with alloy 42
lead frames.
• Heat dissipated from the die faster makes it run cooler
leading to longer life.
• Solder joint reliability vastly improved.
- CTE of Copper (17 ppm/
o
C), matches the CTE of Typical
FR4 PWBs (15-17 ppm/
o
C)
- CTE of Alloy 42 (5 ppm/
o
C), mismatch to CTE of FR4
PWBs (15-17 ppm/
o
C)
• RoHS Version (NiPdAu plating)
- Most preferred for elimination of risk for whisker growth.
The use of copper lead frames inherently allow for better solder joint reliability, tin whisker prevention and
better thermal dissipation. These are three big factors in overall system reliability over time.
Better Solder Joint Reliability
Many systems are expected to operate reliably over broad temperature variations spanning the industrial
(-40
0
C to +85
0
C) and military (-55
0
C to +125
0
C) temperature ranges. System problems can be caused
by the mismatch of thermal coefficients of all system components. Better solder joint reliability is obtained
since the copper lead frame is more
fl
exible, and the CTE of the copper lead frame is better matched with
that of typical FR4 PWBs, than that of Alloy 42. Repeated thermal cycles over a period of time can take a
toll on solder joints, causing cracks and intermittent connections where expansion and contraction of the
lead frame is at a different rate than the FR4 PWB that it is attached to.
Whisker Prevention
The RoHS version of this copper lead frame, with its’ NiPdAu (Nickel-Palladium-Gold) plating, eliminates
the risk of tin whiskers. Microscopic whiskers can grow on a parts’ pins than have tin content in the plat-
ing. Traditionally Alloy 42 lead frames have a Sn or PbSn plating. This plating containing tin, along with
certain environmental conditions can cause these whiskers to grow. Their growth may extend to form a
bridge with another pin on the device, or the whisker may break off and cause a short circuit or even an
explosive power surge on the board. The organization, iNEMI (International Electronics Manufacturing
Initiative) lists the NiPdAu lead plating as the most preferred for elimination of risk for whiskers.
Better Thermal Dissipation
Because copper has a 10X to 12X improvement in thermal conductivity vs. Alloy 42, and since
θ
ja and
θ
jc
characteristics of copper provide up to 3.8X advantage over Alloy 42, more efficient thermal dissipation is
the result. This translates to better heat dissipated away from the chip through the lead frame and PWB,
thus extending the useful life of the die by reducing die junction temperature. Therefore less heat stress
remains in the device, which is a leading cause of non-mechanical failure in a long life application.
1
SDRAM
•
Source: ISSI white paper; “Enhancing Long-Term Reliability with Copper Lead Frames.”
AS4SD8M16
Rev. 1.1 04/10
Micross Components reserves the right to change products or specifications without notice.
3
AS4SD8M16
ENHANCING RELIABILITY WITH COPPER LEAD FRAMES
Thermal Impedance Data - Cu LF vs. Alloy 42, 54 Lead TSOP II
Cu LF
ja
o
C/Watt
64M
128M
256M
512M
62
53
32.3
25.2
Cu LF
jc
o
C/Watt
9
7.8
2.7
2.8
Alloy 42 LF
ja
o
C/Watt
2 Layer
99.1
86.2
81
62.6
Alloy 42 LF
ja
o
C/Watt
4 Layer
70.5
58.9
44
39.2
Alloy 42 LF
jc
o
C/Watt
13.7
11.3
10.3
6.7
SDRAM
ja
Cu LF Advantage
1.6X
1.6X
2.5X
2.5X
jc
Cu LF Advantage
1.5X
1.4X
3.8X
2.4X
With copper lead frames, the die stays cooler, and results in greater component
reliability and longer life. This equates to improved system reliability and lower
service costs and greater system quality confidence.
AS4SD8M16
Rev. 1.1 04/10
Micross Components reserves the right to change products or specifications without notice.
4
AS4SD8M16
PIN DESCRIPTIONS
PIN NUMBER
38
SYMBOL
CLK
TYPE
Input
DESCRIPTION
Clock: CLK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CLK. CLK also
increments the internal burst counter and controls the output
registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SLEF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank) or CLOCK
SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self
refresh modes, where CKE becomes asynchronous until after
exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
Chip Select: CS\ enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS\ is registered HIGH. CS\ provides for external
bank selection on systems with multiple banks. CS\ in considered
part of the command code.
Command Inputs: WE\, CAS\ and RAS\ (along with CS\) define
the command being entered.
Input/Output Mask: DQM is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DWM is sampled HIGH during a WRITE
cycle. The outptu buffers are placed in a High-Z state (two-clock
latency) when DQM is sampled HIGH during a READ cycle.
DQML corresponds to DQ0-DQ7 and DQMH corresponds to
DQ8-DQ15. DQML and DQMH are considered same state when
referenced as DQM.
Bank Address Inputs: BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: A0-A12 are sampled during the ACTIVE
command (row address A0-A12) and READ/WRITE command
(column-address A0-A8; with A10 defining auto precharge) to
select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be prechaged (A10 [HIGH]) or bank
selected by (A10 [LOW]). The address inputs also provide the
op-code during LOAD MODE REGISTER COMMAND.
Data Input/Output: Data bus
SDRAM
37
CKE
Input
19
CS\
Input
16, 17, 18
WE\, CAS\,
RAS\
Input
15, 39
DQML, DQMU
Input
20, 21
BA0, BA1
Input
23-26, 29-34, 22, 35
A0 - A11
Input
2, 4, 5, 7, 8, 10, 11, 13, 42,
44, 45, 47, 48, 50, 51, 53
40, 36
3, 9, 43, 49
6, 12, 46, 52
1, 14, 27
28, 41, 54
AS4SD8M16
Rev. 1.1 04/10
DQ0 - DQ15
NC
V
DD
Q
V
SS
Q
V
DD
V
SS
I/O
---
No Connect: This pin should be left unconnected.
DQ Power: Isolated DQ power to the die for improved noise
Supply
immunity.
DQ Ground: Isolated DQ ground to the die for imporved noise
Supply
immunity.
Supply Power Supply: +3.3V ±0.3V
Supply Ground
Micross Components reserves the right to change products or specifications without notice.
5
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