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MT58LC64K32C5LG-15: 产品描述Cache SRAM, 64KX32, 7ns, CMOS, PQFP100, MS-026, TQFP-100; 产品类别存储存储; 文件大小241KB，共18页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/

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MT58LC64K32C5LG-15概述

Cache SRAM, 64KX32, 7ns, CMOS, PQFP100, MS-026, TQFP-100

MT58LC64K32C5LG-15规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Micron Technology
零件包装代码	QFP
包装说明	MS-026, TQFP-100
针数	100
Reach Compliance Code	not_compliant
ECCN代码	3A991.B.2.A
最长访问时间	7 ns
其他特性	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN
最大时钟频率 (fCLK)	66 MHz
I/O 类型	COMMON
JESD-30 代码	R-PQFP-G100
JESD-609代码	e0
长度	20 mm
内存密度	2097152 bit
内存集成电路类型	CACHE SRAM
内存宽度	32
功能数量	1
端子数量	100
字数	65536 words
字数代码	64000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	64KX32
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LQFP
封装等效代码	QFP100,.63X.87
封装形状	RECTANGULAR
封装形式	FLATPACK, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	235
电源	3.3 V
认证状态	Not Qualified
座面最大高度	1.6 mm
最大待机电流	0.01 A
最小待机电流	3.14 V
最大压摆率	0.2 mA
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3.135 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	GULL WING
端子节距	0.65 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	14 mm

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OBSOLETE

128K x 18, 64K x 32/36

3.3V I/O, PIPELINED, DCD SYNCBURST SRAM

SYNCBURST

SRAM

FEATURES

•

Fast access times: 4.5ns, 5ns, 6ns and 7ns

Fast OE# access times: 4.5ns and 5ns

Single +3.3V +0.3V/-0.165V power supply (V

)

Separate +3.3V +0.3V/-0.165V isolated output buffer

supply (V

SNOOZE MODE for reduced power standby

Common data inputs and data outputs

Individual BYTE WRITE control and GLOBAL WRITE

Three chip enables for simple depth expansion and

address pipelining

Clock-controlled and registered addresses, data I/Os

and control signals

Internally self-timed WRITE cycle

Burst control pin (interleaved or linear burst)

Automatic power-down for portable applications

100-lead TQFP package for high density, high speed

Low capacitive bus loading

x18, x32 and x36 options available

MT58LC128K18C5, MT58LC64K32C5,

MT58LC64K36C5

3.3V Supply, Pipelined, Burst Counter and

Double-Cycle Deselect

100-Pin TQFP*

(SA-1)

*JEDEC-standard MS-026 BHA (LQFP).

OPTIONS

• Clock Cycle Timing

7.5ns/133 MHz

8.5ns/117 MHz

10ns/100 MHz

11ns/90 MHz

15ns/66 MHz

• Configurations

128K x 18

64K x 32

64K x 36

• Package

100-pin TQFP

MARKING

-7.5

-8.5

-10

-11

-15

MT58LC128K18C5

MT58LC64K32C5

MT58LC64K36C5

data inputs, active LOW chip enable (CE#), two additional

chip enables for easy depth expansion (CE2, CE2#), burst

control inputs (ADSC#, ADSP#, ADV#), byte write enables

(BWx#) and global write (GW#).

Asynchronous inputs include the output enable (OE#),

clock (CLK) and snooze enable (ZZ). There is also a burst

mode pin (MODE) that selects between interleaved and

linear burst modes. The data-out (Q), enabled by OE#, is

also asynchronous. WRITE cycles can be from one to two

bytes wide (x18) or from one to four bytes wide (x32/x36)

as controlled by the write control inputs.

Burst operation can be initiated with either address status

processor (ADSP#) or address status controller (ADSC#)

input pins. Subsequent burst addresses can be internally

generated as controlled by the burst advance pin (ADV#).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE cycles.

Individual byte enables allow individual bytes to be written.

During WRITE cycles on the x18 device, BWa# controls

DQa pins and DQPa; BWb# controls DQb pins and DQPb.

During WRITE cycles on the x32 and x36 devices, BWa#

controls DQa pins and DQPa; BWb# controls DQb pins and

DQPb; BWc# controls DQc pins and DQPc; BWd# controls

DQd pins and DQPd. GW# LOW causes all bytes to be

• Part Number Example: MT58LC128K18C5LG-10

GENERAL DESCRIPTION

The Micron SyncBurst SRAM family employs high-

speed, low-power CMOS designs that are fabricated using

an advanced CMOS process.

The MT58LC128K18C5 and MT58LC64K32/36C5 SRAMs

integrate a 128K x 18, 64K x 32 or 64K x 36 SRAM core with

advanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single clock input

(CLK). The synchronous inputs include all addresses, all

128K x 18, 64K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM

Y28.pm6 – Rev. 2/98

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

PowerPC is a trademark of IBM Corporation.

Pentium is a registered trademark of Intel Corporation.

MT58LC64K32C5LG-15相似产品对比

	MT58LC64K32C5LG-15	MT58LC128K18C5LG-15	MT58LC64K36C5LG-10	MT58LC128K18C5LG-11	MT58LC64K36C5LG-11	MT58LC128K18C5LG-10	MT58LC64K32C5LG-10
描述	Cache SRAM, 64KX32, 7ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 128KX18, 7ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 64KX36, 5ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 128KX18, 6ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 64KX36, 6ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, MS-026, TQFP-100	Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, MS-026, TQFP-100
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合
厂商名称	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology
零件包装代码	QFP	QFP	QFP	QFP	QFP	QFP	QFP
包装说明	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100	MS-026, TQFP-100
针数	100	100	100	100	100	100	100
Reach Compliance Code	not_compliant	_compli	not_compliant	unknown	unknown	not_compliant	_compli
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	7 ns	7 ns	5 ns	6 ns	6 ns	5 ns	5 ns
其他特性	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN	BURST CONTROL; SELF TIMED WRITE CYCLE; REGISTER ADDRESS; BYTE WRITE CONTROL; AUTOMATIC POWER DOWN
最大时钟频率 (fCLK)	66 MHz	66 MHz	100 MHz	90 MHz	90 MHz	100 MHz	100 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609代码	e0	e0	e0	e0	e0	e0	e0
长度	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm
内存密度	2097152 bit	2359296 bi	2359296 bit	2359296 bit	2359296 bit	2359296 bit	2097152 bi
内存集成电路类型	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
内存宽度	32	18	36	18	36	18	32
功能数量	1	1	1	1	1	1	1
端子数量	100	100	100	100	100	100	100
字数	65536 words	131072 words	65536 words	131072 words	65536 words	131072 words	65536 words
字数代码	64000	128000	64000	128000	64000	128000	64000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	64KX32	128KX18	64KX36	128KX18	64KX36	128KX18	64KX32
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP	LQFP
封装等效代码	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
电源	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
最大待机电流	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A	0.01 A
最小待机电流	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
最大压摆率	0.2 mA	0.2 mA	0.3 mA	0.25 mA	0.25 mA	0.3 mA	0.3 mA
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
宽度	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
峰值回流温度（摄氏度）	235	-	235	235	235	235	235
处于峰值回流温度下的最长时间	30	-	30	30	30	30	30

MT58LC64K32C5LG-15

MT58LC64K32C5LG-15概述

MT58LC64K32C5LG-15规格参数

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MT58LC64K32C5LG-15相似产品对比

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