HY62V8200B Series
256Kx8bit CMOS SRAM
DESCRIPTION
The HY62V8200B is a high speed, low power and
2M bit CMOS SRAM organized as 262,144 words
by 8bit. The HY62V8200B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particularly well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup( LL-part )
-. 2.0V(min) data retention
•
Standard pin configuration
-. 32-sTSOPI-8X13.4, 32-TSOPI -8X20
(Standard and Reversed)
Product
Voltage
Speed
Operation
No.
(V)
(ns)
Current/Icc(mA)
HY62V8200B
3.0~3.6
70/85/100
5
HY62V8200B-E 3.0~3.6
70/85/100
5
HY62V8200B-I
3.0~3.6
70/85/100
5
Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
Standby
Current(uA)
25
25
25
Temperature
(°C)
0~70
-25~85(E)
-40~85(I)
PIN CONNECTION
A11
A9
A8
A13
/WE
CS2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
A4
A5
A6
A7
A12
A14
A16
A17
Vcc
A15
CS2
/WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
DQ4
DQ5
DQ6
DQ7
DQ8
/CS1
A10
/OE
sTSOPI/TSOPI
(Standard)
sTSOPI/TSOPI
(Reversed)
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
A0 ~ A17
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Address Input
Data Input/Output
Power(3.0V~3.6V)
Ground
A0
BLOCK DIAGRAM
ROW
DECODER
SENSE AMP
ADD INPUT BUFFER
I/O1
COLUMNDECODER
DATA I/O
BUFFER
MEMORY ARRAY
256K x 8
WRITE DRIVER
A17
I/O8
/CS1
/CS2
/WE
/OE
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 /Jun. 2000
Hyundai Semiconductor
CONTROL
LOGIC
HY62V8200B Series
ORDERING INFORMATION
Part No.
Speed
Power
Temp.
HY62V8200BLLT1
70/85/100
LL-part
HY62V8200BLLR1
70/85/100
LL-part
HY62V8200BLLST
70/85/100
LL-part
HY62V8200BLLSR
70/85/100
LL-part
HY62V8200BLLT1-E
70/85/100
LL-part
E
HY62V8200BLLR1-E
70/85/100
LL-part
E
HY62V8200BLLST-E
70/85/100
LL-part
E
HY62V8200BLLSR-E 70/85/100
LL-part
E
HY62V8200BLLT1-I
70/85/100
LL-part
I
HY62V8200BLLR1-I
70/85/100
LL-part
I
HY62V8200BLLST-I
70/85/100
LL-part
I
HY62V8200BLLSR-I
70/85/100
LL-part
I
Note 1. Blank : Commercial, E : Extended, I : Industrial
Package
TSOPI(Standard)
TSOPI(Reversed)
Smaller TSOPI(Standard)
Smaller TSOPI(Reversed)
TSOPI(Standard)
TSOPI(Reversed)
Smaller TSOPI(Standard)
Smaller TSOPI(Reversed)
TSOPI(Standard)
TSOPI(Reversed)
Smaller TSOPI(Standard)
Smaller TSOPI(Reversed)
ABSOLUTE MAXIMUM RATING (1)
Symbol
V
IN,
V
OUT
V
CC
T
A
Parameter
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to
Vss
Operating Temperature
Rating
-0.2 to 3.9
-0.2 to 4.0
0 to 70
-25 to 85
-40 to 85
-55 to 150
1.0
50
260
•
5
Unit
V
V
°C
°C
°C
°C
W
mA
°C•sec
Remark
HY62V8200B
HY62V8200B-E
HY62V8200B-I
T
STG
Storage Temperature
P
D
Power Dissipation
I
OUT
Data Output Current
T
SOLDER
Lead Soldering Temperature & Time
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
H
X
L
L
L
CS2
X
L
H
H
H
/WE
X
X
H
H
L
/OE
X
X
H
L
X
Mode
Deselected
Deselected
Output Disabled
Read
Write
I/O
High-Z
High-Z
High-Z
Dout
D
IN
Power
Standby
Standby
Active
Active
Active
Note :
1. H=V
IH
, L=V
IL
, X=don't care(V
IH
or
V
IL
)
Rev.02 /Jun. 2000
2
HY62V8200B Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High
Voltage
Input Low Voltage
Min.
3.0
0
2.2
-0.2
(1)
Typ.
3.3
0
-
-
Max.
3.6
0
Vcc+0.2
0.4
Unit
V
V
V
V
Note
1. V
IL
= -1.5V for pulse width less than 30ns
DC ELCTRICAL CHARACTERISTICS
Vcc= 3.0~3.6V, T
A
= 0°C to 70°C/ -25°C to 85°C (E)/ -40°C to 85°C (I), unless otherwise specified
Sym.
Parameter
Test Condition
Min. Typ.
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
-1
-
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS1 = V
IH
or
CS2 = V
IL
or
/
OE
=
V
IH
or /WE =
V
IL
Icc
Operating Power Supply
/CS1 = V
IL
, CS2 = V
IH,
-
-
Current
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
I
CC1
Average Operating
Min Duty Cycle = 100%
,
70ns
-
-
Current
/CS1 = V
IL
CS2 = V
IH
85ns
-
-
V
IN
= V
IH
or V
IL
100ns
-
-
Cycle time = 1us, I
I/O =
0mA,
-
-
/CS1
¡ Â
0.2V, CS2
¡ Ã
Vcc - 0.2V
V
IN
¡ Â
0.2V or V
IN
¡ Ã
Vcc – 0.2V
I
SB
TTL Standby Current
/CS1 = V
IH
or CS2 = V
IL
-
-
(TTL Input)
-
I
SB1
Standby
HY62V8200B
/CS1 > Vcc - 0.2V, CS2 > 0.2V or
-
-
Current
HY62V8200B-E CS2 > Vcc - 0.2V
-
-
(CMOS Input) HY62V8200B-I
-
-
V
OL
Output Low Voltage
I
OL
= 2.1mA
-
-
V
OH
Output High Voltage
I
OH =
-1mA
2.2
-
Note : Typical values are at Vcc = 3.3V, T
A
= 25°C
Max.
1
1
Unit
uA
uA
5
60
50
50
6
mA
mA
mA
mA
mA
0.5
25
25
25
0.4
-
mA
uA
uA
uA
V
V
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance
C
OUT
Output Capacitance
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
8
10
Unit
pF
pF
Note : These parameters are sampled and not 100% tested
Rev.02 /Jun. 2000
3
HY62V8200B Series
AC CHARACTERISTICS
Vcc= 2.7V~3.6V, T
A
= 0°C to 70°C/ -25°C to 85°C(E)/ -40°C to 85°C(I), unless otherwise specified
-70
-85
-10
# Symbol
Parameter
Min.
Max. Min. Max. Min. Max.
READ CYCLE
1
tRC
Read Cycle Time
70
-
85
-
100
-
2
tAA
Address Access Time
-
70
-
85
-
100
3
tACS
Chip Select Access Time
-
70
-
85
-
100
4
tOE
Output Enable to Output Valid
-
40
-
45
-
50
5
tCLZ
Chip Select to Output in Low Z
10
-
10
-
10
-
6
tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
7
tCHZ
Chip Deselection to Output in High Z
0
20
0
25
0
30
8
tOHZ
Out Disable to Output in High Z
0
20
0
25
0
30
9
tOH
Output Hold from Address Change
15
-
15
-
15
-
WRITE CYCLE
10 tWC
Write Cycle Time
70
-
85
-
100
-
11 tCW
Chip Selection to End of Write
60
-
70
-
80
-
12 tAW
Address Valid to End of Write
60
-
70
-
80
-
13 tAS
Address Set-up Time
0
-
0
-
0
-
14 tWP
Write Pulse Width
50
-
60
-
70
-
15 tWR
Write Recovery Time
0
-
0
-
0
-
16 tWHZ
Write to Output in High Z
0
20
0
25
0
30
17 tDW
Data to Write Time Overlap
35
-
35
-
40
-
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
19 tOW
Output Active from End of Write
5
-
5
-
5
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
T
A
= 0°C to 70°C / -25°C to 85°C (E)/ -40°C to 85°C (I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
CL = 100pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : 1 Including jig and scope capacitance
Rev.02 /Jun. 2000
4
HY62V8200B Series
TIMING DIAGRAM
READ CYCLE 1(Note1,4)
tRC
ADDR
tAA
tACS
/CS1
tOH
CS2
tCHZ
(3)
/OE
tOLZ
(3)
Data
Out
High-Z
tCLZ
(3)
Data Valid
tOE
tOHZ
(3)
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
Data
Out
Previous Data
Data Valid
tOH
READ CYCLE 3(Note 1,2,4)
/CS1
CS2
tACS
tCLZ
(3)
Data
Out
Data Valid
tCHZ
(3)
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low /CS1 and CS2 are in active status.
2. /OE = V
IL
3. Transition is measured
¡ ¾
00mV from steady state voltage.
2
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Rev.02 /Jun. 2000
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
