HN29V128A1A (3.3 V/×8)
HN29V128A0A (3.3 V/×16)
HN29A128A1A (1.8 V/×8)
HN29A128A0A (1.8 V/×16)
128M superAND Flash Memory
(with internal sector management)
REJ03C0031-0300Z
Rev. 3.00
Jun. 09, 2004
Description
The HN29V128A1A, HN29V128A0A, HN29A128A1A, and HN29A128A0A Series is a CMOS flash
memory, which uses cost effective and high performance AND type multi-level memory cell technology.
Current AND flash memory requires us to support complicated operations such as sector management for
defect sector and error check correction. But this series doesn’t need such operations. Beside it supports
wear leveling function, which is sector replacement function in case of that certain sector, reaches certain
erase/write times. And power-on-auto-read function is available. It enables to read the data of the lowest
sector(2k byte) without command and address data input when power is on.
Note: This product is authorized for using consumer application such as cellular phone,
Therefore, please contact Renesas Technology’s sales office before using other applications.
Rev.3.00, Jun.09.2004, page 1 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Features
•
On-board single power supply (V
CC
): V
CC
= 2.7 V to 3.6 V (HN29V128A1A/HN29V128A0A)
: V
CC
= 1.70 V to 1.95 V (HN29A128A1A/HN29A128A0A)
•
Operating temperature range: Ta = 0 to
+70 °C
•
Program/erase, rewrite endurance
10
5
times
•
Access time
First access
80
µs
(typ) (3.3 V,
×8/×16)
150
µs
(typ) (1.8 V,
×8/×16)
Serial read cycle
50 ns (min) (3.3 V,
×8/×16)
100 ns (min) (1.8 V,
×8/×16)
maximum transfer rate (sequential read)
20.0 Mbyte/s (3.3 V,
×8)
40.0 Mbyte/s (3.3 V,
×16)
10.0 Mbyte/s (1.8 V,
×8)
20.0 Mbyte/s (1.8 V,
×16)
•
Program time
1.2 ms (typ) /sector (2048 byte) (3.3 V,
×8/×16)
2.0 ms (typ) /sector (2048 byte) (1.8 V,
×8/×16)
•
Erase time
2.2 ms (typ) /sector (2048 byte) (3.3 V,
×8/×16)
3.5 ms (typ) /sector (2048 byte) (1.8 V,
×8/×16)
•
Rewrite time
2.2 ms (typ) /sector (2048 byte) (3.3 V,
×8/×16)
3.5 ms (typ) /sector (2048 byte) (1.8 V,
×8/×16)
Rev.3.00, Jun.09.2004, page 2 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
•
Low power dissipation (3.3 V and 1.8 V)
Standby current
I
CCS1
= 1 mA (max)
I
CCS2
= 50
µA
(max) (CMOS level)
I
CCS3
= 10
µA
(max) (3.3 V), 15µA (max) (1.8 V) (deep standby)
Serial read operation current
I
CC1
= 30 mA (max)
Program/erase/rewrite operation current
I
CC2/3/4
= 60 mA (max) (program/erase/rewrite)
•
Sector management
Following functions are build-in flash memory component.
Sector management:
If certain sector had been damaged, it would be replaced by the spare sector automatically.
Always 100% of sector number are available up to 10
5
erase/write cycles per device.
Error check and correction:
ECC code is generated at the time of programming, and data error is checked at the time of read
operation. If data error occurs, the data will be corrected automatically.
(ECC: 1-byte error correction, 2-byte error detection per 512byte page)
Wear leveling:
To avoid erase/program/rewrite operation converge on the particular physical sector, The number of
erase/program/rewrite operation will be leveled automatically by changing internal logical sector
address.
•
Package line up
CSP: CSP 95-bump (TBP-95V)
Ordering Information
Type No.
HN29V128A1ABP-5E
HN29V128A0ABP-5E
HN29A128A1ABP-8E
HN29A128A0ABP-8E
Operating voltage (V
CC
) Organization
3.3 V
3.3 V
1.8 V
1.8 V
×8
×16
×8
×16
Package
10.0
×
11.50 mm
2
, 95-bump
0.8 mm ball pitch CSP (TBP-95V)
Lead free
Rev.3.00, Jun.09.2004, page 3 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Pin Arrangement
95-bump CSP
95-bump CSP
1
A
B
C
D
E
F
G
H
J
K
L
M
DU
DU
DU
DU
2
DU
DU
DU
DU
DU
3
4
5
6
7
8
9
10
11
DU
DU
12
DU
DU
DU
DU
WE
V
SS
DU
DU
R/B
DSE
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
PRE
I/O3
DU
DU
DU
DU
DU
V
SS
I/O8
DU
I/O7
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
DU
I/O15
MRES
I/O13 I/O6
I/O5
DU
I/O1
DU
DU
DU
I/O11
I/O9
DU
V
SS
I/O14 I/O16
DU
V
CC
DU
DU
DU
DU
DU
DU
WP
DU
CLE
ALE
I/O4 I/O12
I/O2 I/O10
DU
RE
DU
CE
(TOP View)
Rev.3.00, Jun.09.2004, page 4 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Pin Description
Name
I/O1 to I/O8
I/O9 to I/O16
CLE
ALE
CE
RE
WE
WP
R/B
PRE
MRES
DSE
V
CC
V
SS
DU
Description
Command, address, data input/output
Data input/output (×8 device: DU)
Command latch enable
Address latch enable
Chip enable
Read enable
Write enable
Write protect
Ready/busy
Power on auto read enable
Master reset output
Deep standby enable
Power supply
Ground
Don’t use
Note: 1. All V
SS
pins should be connected respectively.
Rev.3.00, Jun.09.2004, page 5 of 49
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