256MB, 512MB (x64, DR): 200-Pin DDR SDRAM SODIMM

Features

DDR SDRAM SODIMM

MT8VDDT3264HD – 256MB

1

MT8VDDT6464HD – 512MB

For component data sheets, refer to Micron’s Web site:

www.micron.com

Features

• 200-pin, small-outline dual in-line memory module

(SODIMM)

• Fast data transfer rates: PC2100, PC2700, or PC3200

• 256MB (32 Meg x 64), 512MB (64 Meg x 64)

• V

DD

= V

DD

Q = +2.5V

(-40B: V

DD

= V

DD

Q = +2.6V)

• V

DDSPD

= +2.3V to +3.6V

• 2.5V I/O (SSTL_2-compatible)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/

received with data—that is, source-synchronous

data capture

• Differential clock inputs (CK and CK#)

• Multiple internal device banks for concurrent

operation

• Selectable burst lengths (BL): 2, 4, or 8

• Auto precharge option

• Auto refresh and self refresh modes: 7.8125µs

maximum average periodic refresh interval

• Serial presence-detect (SPD) with EEPROM

• Selectable CAS latency (CL) for maximum

compatibility

• Dual rank

• Gold edge contacts

Figure 1:

200-Pin SODIMM (MO-224)

PCB height: 31.75mm (1.25in)

Options

•

Operating temperature

2

Marking

–

Commercial (0°C

≤

T

A

≤

+70°C)

None

–

Industrial (–40°C

≤

T

A

≤

+85°C)

I

• Package

–

200-pin DIMM (standard)

G

–

200-pin DIMM (lead-free)

Y

• Memory clock, speed, CAS latency

–

5.0ns (200 MHz), 400 MT/s, CL = 3

-40B

–

6.0ns (167 MHz), 333 MT/s, CL = 2.5

-335

1

–

7.5ns (133 MHz), 266 MT/s, CL = 2

-26A

1

–

7.5ns (133 MHz), 266 MT/s, CL = 2.5

-265

Notes: 1. Not recommended for new designs.

2. Contact Micron for industrial temperature

module offerings.

Table 1:

Speed

Grade

-40B

-335

-26A

-265

Key Timing Parameters

Industry

Nomenclature

PC3200

PC2700

PC2100

Notes:

Data Rate (MT/s)

CL = 3

400

–

CL = 2.5

333

266

CL = 2

266

200

t

RCD

(ns)

15

18

20

RP

(ns)

15

18

20

t

RC

(ns)

55

60

65

t

Notes

1

1. The values of

t

RCD and

t

RP for -335 modules show 18ns to align with industry specifications;

actual DDR SDRAM device specifications are 15ns.

PDF: 09005aef80765fab/Source: 09005aef806e1d28

DD8C32_64x64HD.fm - Rev. E 11/08 EN

1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

256MB, 512MB (x64, DR): 200-Pin DDR SDRAM SODIMM

Features

Table 2:

Parameter

Refresh count

Row address

Device bank address

Device configuration

Column address

Module rank address

Addressing

256MB

8K

8K (A0–A12)

4 (BA0, BA1)

256Mb (16 Meg x 16)

512 (A0–A8)

2 (S0#, S1#)

512MB

8K

8K (A0–A12)

4 (BA0, BA1)

512Mb (32 Meg x 16)

1K (A0–A9)

2 (S0#, S1#)

Table 3:

Part Numbers and Timing Parameters – 256MB

Base device: MT46V16M16,

1

256Mb DDR SDRAM

Module

Density

256MB

Module

Bandwidth

3.2 GB/s

2.7 GB/s

2.1 GB/s

Memory Clock/

Data Rate

5.0ns/400 MT/s

6.0ns/333 MT/s

7.5ns/266 MT/s

Clock Cycles

(CL-

t

RCD-

t

RP)

3-3-3

2.5-3-3

2-3-3

2.5-3-3

Part Number

2

MT8VDDT3264HDG-40B__

MT8VDDT3264HDY-40B__

MT8VDDT3264HDG-335__

MT8VDDT3264HDY-335__

MT8VDDT3264HDG-26A__

MT8VDDT3264HDG-265__

MT8VDDT3264HDY-265__

Configuration

32 Meg x 64

Table 4:

Part Numbers and Timing Parameters – 512MB

Base device: MT46V32M16,

1

512Mb DDR SDRAM

Module

Density

512MB

Module

Bandwidth

3.2 GB/s

2.7 GB/s

2.1 GB/s

Memory Clock/

Data Rate

5.0ns/400 MT/s

6.0ns/333 MT/s

7.5ns/266 MT/s

Clock Cycles

(CL-

t

RCD-

t

RP)

3-3-3

2.5-3-3

Part Number

2

MT8VDDT6464HDG-40B__

MT8VDDT6464HDY-40B__

MT8VDDT6464HDG-335__

MT8VDDT6464HDY-335__

MT8VDDT6464HDG-265__

MT8VDDT6464HDY-265__

Notes:

Configuration

64 Meg x 64

1. Data sheets for the base devices can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and

PCB revisions. Consult factory for current revision codes.

Example: MT8VDDT6464HDY-335F2.

PDF: 09005aef80765fab/Source: 09005aef806e1d28

DD8C32_64x64HD.fm - Rev. E 11/08 EN

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256MB, 512MB (x64, DR): 200-Pin DDR SDRAM SODIMM

Pin Assignments and Descriptions

Table 5:

Pin Assignments

200-Pin SODIMM Front

Pin Symbol Pin Symbol

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

V

REF

V

SS

DQ0

DQ1

V

DD

DQS0

DQ2

V

SS

DQ3

DQ8

V

DD

DQ9

DQS1

V

SS

DQ10

DQ11

V

DD

CK0

CK0#

V

SS

DQ16

DQ17

V

DD

DQS2

DQ18

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

V

SS

DQ19

DQ24

V

DD

DQ25

DQS3

V

SS

DQ26

DQ27

V

DD

NC

V

SS

NC

V

DD

NC

V

SS

NC

V

DD

CKE1

NC

A12

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

Symbol Pin Symbol

A9

V

SS

A7

A5

A3

A1

V

DD

A10

BA0

WE#

S0#

NC

V

SS

DQ32

DQ33

V

DD

DQS4

DQ34

V

SS

DQ35

DQ40

V

DD

DQ41

DQS5

V

SS

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

DQ42

DQ43

V

DD

V

DD

V

SS

V

SS

DQ48

DQ49

V

DD

DQS6

DQ50

V

SS

DQ51

DQ56

V

DD

DQ57

DQS7

V

SS

DQ58

DQ59

V

DD

SDA

SCL

V

DDSPD

NC

200-Pin SODIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

V

REF

V

SS

DQ4

DQ5

V

DD

DM0

DQ6

V

SS

DQ7

DQ12

V

DD

DQ13

DM1

V

SS

DQ14

DQ15

V

DD

V

DD

V

SS

V

SS

DQ20

DQ21

V

DD

DM2

DQ22

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

V

SS

DQ23

DQ28

V

DD

DQ29

DM3

V

SS

DQ30

DQ31

V

DD

NC

V

SS

NC

V

DD

NC

V

SS

V

SS

V

DD

V

DD

CKE0

NC

A11

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

A8

V

SS

A6

A4

A2

A0

V

DD

BA1

RAS#

CAS#

S1#

NC

V

SS

DQ36

DQ37

V

DD

DM4

DQ38

V

SS

DQ39

DQ44

V

DD

DQ45

DM5

V

SS

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

DQ46

DQ47

V

DD

CK1#

CK1

V

SS

DQ52

DQ53

V

DD

DM6

DQ54

V

SS

DQ55

DQ60

V

DD

DQ61

DM7

V

SS

DQ62

DQ63

V

DD

SA0

SA1

SA2

NC

PDF: 09005aef80765fab/Source: 09005aef806e1d28

DD8C32_64x64HD.fm - Rev. E 11/08 EN

3

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256MB, 512MB (x64, DR): 200-Pin DDR SDRAM SODIMM

Pin Assignments and Descriptions

Table 6:

Pin Descriptions

Symbol

A0–A12

Type

Input

Description

Address inputs:

Provide the row address for ACTIVE commands, and the

column address and auto precharge bit (A10) for READ/WRITE commands, to

select one location out of the memory array in the respective device bank. A10

sampled during a PRECHARGE command determines whether the PRECHARGE

applies to one device bank (A10 LOW, device bank selected by BA0 and BA1)

or all device banks (A10 HIGH). The address inputs also provide the op-code

during a MODE REGISTER SET command. BA0 and BA1 define which mode

register (mode register or extended mode register) is loaded during the LOAD

MODE REGISTER command.

Bank address:

BA0 and BA1 define the device bank to which an ACTIVE,

READ, WRITE, or PRECHARGE command is being applied.

Clock:

CK and CK# are differential clock inputs. All control, command, and

address input signals are sampled on the crossing of the positive edge of CK

and the negative edge of CK#. Output data (DQ and DQS) is referenced to the

crossings of CK and CK#.

Clock enable:

CKE enables (registered HIGH) and CKE disables (registered

LOW) the internal clock, input buffers, and output drivers.

Input data mask:

DM is an input mask signal for write data. Input data is

masked when DM is sampled HIGH, along with that input data, during a write

access. DM is sampled on both edges of DQS. Although DM pins are input-only,

the DM loading is designed to match that of DQ and DQS pins.

Command inputs:

RAS#, CAS#, and WE# (along with S#) define the command

being entered.

Chip selects:

S# enables (registered LOW) and disables (registered HIGH) the

command decoder.

Presence-detect address inputs:

These pins are used to configure the SPD

EEPROM address range on the I

2

C bus.

Serial clock for SPD EEPROM:

SCL is used to synchronize the presence-detect

data transfer to and from the module.

Data input/output:

Data bus.

Data strobe:

Output with read data. Edge-aligned with read data. Input with

write data. Center-aligned with write data. Used to capture data.

Serial data:

SDA is a bidirectional pin used to transfer addresses and data into

and out of the presence-detect portion of the module.

Power supply:

+2.5V ±0.2V (-40B: +2.6V ±0.1V).

Serial EEPROM power supply:

+2.3V to +3.6V.

SSTL_2 reference voltage (V

DD

/2).

Ground.

No connect:

These pins are not connected on the module.

BA0, BA1

CK0, CK0#,

CK1, CK1#

Input

CKE0, CKE1

DM0–DM7

Input

RAS#, CAS#, WE#

S0#, S1#

SA0–SA2

SCL

DQ0–DQ63

DQS0–DQS7

SDA

V

DD

V

DDSPD

V

REF

V

SS

NC

Input

I/O

Supply

–

PDF: 09005aef80765fab/Source: 09005aef806e1d28

DD8C32_64x64HD.fm - Rev. E 11/08 EN

4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

256MB, 512MB (x64, DR): 200-Pin DDR SDRAM SODIMM

Functional Block Diagram

Figure 2:

S1#

S0#

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

UDQS

UDM

DQ

LDQS

LDM

DQ

CS#

Functional Block Diagram

U1

LDQS

LDM

DQ

UDQS

UDM

DQ

CS#

DQS4

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

CS#

U5

UDQS

UDM

DQ

LDQS

LDM

DQ

U3

LDQS

LDM

DQ

UDQS

UDM

DQ

CS#

U7

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

CS#

UDQS

UDM

DQ

LDQS

LDM

DQ

U2

LDQS

LDM

DQ

UDQS

UDM

DQ

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U6

UDQS

UDM

DQ

LDQS

LDM

DQ

CS#

U4

LDQS

LDM

DQ

UDQS

UDM

DQ

U8

BA0–BA1

A0–A12

RAS#

CAS#

WE#

CKE0

CKE1

DDR SDRAM

DDR SDRAM Rank 0

DDR SDRAM Rank 1

Rank 0 = U1–U4

Rank 1 = U5–U8

V

DDSPD

SPD EEPROM

DDR SDRAM

U9

SCL

SPD EEPROM

WP A0 A1 A2

SDA

V

DD

V

REF

V

SS

V

SS

SA0 SA1 SA2

CK0

CK0#

DDR SDRAM

U1, U2, U5, U6

CK1

CK1#

DDR SDRAM

U3, U4, U7, U8

CK2

CK2#

PDF: 09005aef80765fab/Source: 09005aef806e1d28

DD8C32_64x64HD.fm - Rev. E 11/08 EN

5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Micron Technology
零件包装代码	MODULE
包装说明	DIMM,
针数	200
Reach Compliance Code	unknown
ECCN代码	EAR99
访问模式	DUAL BANK PAGE BURST
最长访问时间	0.7 ns
其他特性	AUTO/SELF REFRESH
JESD-30 代码	R-XDMA-N200
JESD-609代码	e0
内存密度	4294967296 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	64
功能数量	1
端口数量	1
端子数量	200
字数	67108864 words
字数代码	64000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	64MX64
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
自我刷新	YES
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.5 V
标称供电电压 (Vsup)	2.6 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	NO LEAD
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED

MT8VDDT6464HDG-40BXX

MT8VDDT6464HDG-40BXX概述

MT8VDDT6464HDG-40BXX规格参数

文档预览

推荐资源